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US 7,352,826 B2Granted
Analog delay circuit
AssigneeIntel Corporation
InventorAnush A. Krishnaswami
Life of this patent
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Abstract
An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.
Claims16
An analog delay circuit to impart a group delay in an analog input signal, the analog delay circuit comprising:
- an input stage to receive the analog input signal;
- an output stage to provide the analog output signal substantially comprising a version of the analog input signal delayed according to the group delay;
- and
- an intermediate stage comprising:
- a capacitor to impart at least a portion of the group delay to the analog output signal;
- and
- a buffer circuit coupled between the capacitor and the input stage to substantially remove at least a portion of a capacitive load at an input to the intermediate stage;
- a first capacitor coupled to the first differential input terminal through a first buffer circuit;
- a second capacitor coupled to the second differential input terminal through a second buffer circuit;
- and
- a differential amplifier to provide a differential output signal to the output stage in response to a differential input signal applied to the first and second differential input terminals;
- wherein the differential amplifier comprises a first DC current source and wherein the first and second buffer circuits each comprises a second DC current source having a magnitude exceeding a magnitude of first DC current source.
9 more elements
A system comprising:
- a receiver adapted to process the analog input signal from a transmission medium, the receiver comprising:
- a plurality of delay circuits to generate a plurality of analog signal taps, each delay circuit to generate a corresponding analog signal tap from the analog input signal according to a group delay;
- a multi-tap filter to apply each of a plurality of coefficients to a corresponding one of the analog signal taps to provide an equalized analog signal;
- a clock and data recovery circuit to recover temporally spaced symbols from the equalized analog signal as a serial data signal;
- and
- a deserializer to provide a parallel data signal in response to the serial data signal, wherein each of the delay circuits comprises:
- an input stage to receive the analog input signal;
- an output stage to provide the analog signal tap associated with the delay circuit substantially comprising a version of the analog input signal delayed according to the group delay;
- and
- an intermediate stage comprising a capacitor to impart at least a portion of the group delay to the analog signal tap, a buffer circuit coupled between the capacitor and the input stage to substantially remove at least a portion of a capacitive load at an input to the intermediate stage, a first capacitor coupled to the first differential input terminal through a first buffer circuit, a second capacitor coupled to the second differential input terminal through a second buffer circuit and wherein the differential amplifier comprises a first DC current source, and a differential amplifier to provide a differential output signal to the output stage in response to a differential input signal applied to the first and second differential input terminals;
- wherein an input to each intermediate stage of each delay circuit comprises first and second differential input terminals;
- and wherein the differential amplifier comprises a first DC current source and wherein the first and second buffer circuits each comprises a second DC current source having a magnitude exceeding a magnitude of the first DC current source.
9 more elements
Dependencies are inferred from the claim text.