Data oversampling via clock and data interpolation
AssigneeAgilent Technologies, Inc.
InventorReed Glenn Wood, Jr.
Life of this patent
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Abstract
An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.
Claims9
A data recovery system, comprising:
- first and second data sampling elements;
- a clock interpolator to receive a first differential clock and output a second differential clock, said first differential clock operating the first data sampling element, and said second differential clock operating the second data sampling element;
- a data interpolator to receive and output differential data signals, said received differential data signal being sampled by the first data sampling element, and said output differential data signal being sampled by the second data sampling element;
- and
- a mechanism to steer current between first and second nodes, the first node being coupled to bias an input differential pair of the clock interpolator and a delayed differential pair of the data interpolator, and the second node being coupled to bias an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator.
A method for providing an oversampling delay between clock and data signals, comprising:
- steering a current between first and second nodes, said first node being coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator, and said second node being coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator;
- providing first clock and data signals to a first data sampling element and, respectively, to said clock and data interpolators;
- and
- providing second clock and data signals, respectively output from the clock and data interpolators, to a second data sampling element.
Dependencies are inferred from the claim text.