Multiple calendar schedule reservation structure and method
AssigneeIntel Corporation
InventorsDonald F. Hooper, Suresh Kalkunte
Life of this patent
Estimating the term…
Abstract
A machine-based method includes scheduling data units into respective time slots of reservation groups by representing the time slots in a base vector. The time slots of each of the reservation groups corresponds to a contiguous block in the base vector. Groups of time slots are represented in a higher-level vector having fewer elements than the base vector.
Claims48
A computer-based method, comprising:
- scheduling data units for transmission within a time interval corresponding to one or more of a plurality of time slots represented by elements in a first-level vector, the time slots of the interval corresponding to selected elements of a contiguous block of elements in the first-level vector;
- representing groups of elements in the first-level vector by respective elements in a second-level vector having fewer elements than the first-level vector, with the quantity of elements included in the first-level vector being equal to the quantity of elements included in the second-level vector, scaled by a scaling factor;
- and
- representing groups of the groups of elements in a third-level vector having fewer elements than the second-level vector.
A traffic shaping method, comprising:
- scheduling data units for transmission within a time interval represented by one or of a plurality of time slots, the time slots of the interval corresponding to selected time slots of a contiguous block of time slots;
- and
- representing the time slots in one or more hierarchical reservation vectors, the one or more hierarchical reservation vectors including;
- a first-level vector including one or more bits that each represent one time slot;
- and
- a second-level vector including one or more bits that each represent a group of time slots represented in the first-level vector
- wherein the one or more hierarchical reservation vectors further include a third-level vector including one or more bits that each represent a plurality of the groups of time slots represented in the second-level vector.
A computer-readable medium embodied with a computer program to perform a method of storing executable instructions for traffic shaping, comprising:
- schedule data units for transmission within a time interval represented by one or more of a plurality of time slots, the time slots of the interval corresponding to selected time slots of a contiguous block of time slots;
- and
- represent the time slots in one or more hierarchical reservation vectors, the one or more hierarchical reservation vectors including:
- a first-level vector including one or more bits that each represent one time slot;
- and
- a second-level vector including one or more bits that each represent a group of time slots represented in the first-level vector;
- wherein the one or more hierarchical reservation vectors further includes a third-level vector including one or more bits that each represent a plurality of the groups of time slots represented in the second-level vector.
A router system, comprising
- circuitry configured to schedule data units for transmission within a time interval represented by one or more of a plurality of time slots, the time slots of the interval corresponding to selected time slots of a contiguous block of time slots;
- and
- circuitry configured to represent the time slots in one or more hierarchical reservation vectors, the one or more hierarchical reservation vectors including:
- a first-level vector including one or more bits that each represent one time slot;
- and
- a second-level vector including one or more bits that each represent a group of time slots represented in the first-level vector;
- wherein the one or more hierarchical reservation vectors further include a third-level vector including one or more bits that each represent a plurality of the groups of time slots represented in the second-level vector.
A router system within a network of computers, comprising
- circuitry configured to schedule data units received from the network of computers for transmission within a time interval represented by one or more of a plurality of time slots;
- circuitry configured to represent the time slots in one or more hierarchical reservation vectors, the one or more hierarchical reservation vectors including:
- a first-level vector including one or more bits that each represent one time slot wherein the plurality of time slots correspond to a transmission cycle that repeats;
- a second-level vector including one or more bits that each represent a group of time slots represented in the first-level vector;
- a third-level vector including one or more bits that each represent a plurality of the groups of time slots represented in the second-level vector;
- and
- circuitry configured to:
- identify, within the third-level vector, a select plurality of groups having an available time slot;
- identify, within the second-level vector, a select group of time slots, as chosen from the select plurality of groups, that includes the available time slot;
- identify, within the first-level vector, the available time slot, as chosen from the select group of time slots;
- calculate a could-send time based on a maximum data transfer rate, and designate a first available time slot as a could-send time slot;
- calculate a must-send time based on a minimum data transfer rate, and designate a second available time slot as a must-send time slot;
- reserve a range of time slots corresponding to a range of bits within a block of bits, the range of bits occurring between a bit representing the must-send time slot and a bit representing the could-send time slot, if it is determined that the range of bits is contiguous within the block when representing the must-send time slot as chronologically after the could-send time slot;
- and
- reserve a first range of time slots corresponding to a first range of bits within a block of bits, the first range of bits occurring between a bit representing a first end time slot represented in the block and a bit representing the must-send time slot;
- and a second range of time slots corresponding to a second range of bits within the block, the second range of bits occurring between a bit representing the could-send time slot and a bit representing a second end time slot represented in the block, if it is determined that the range of bits wraps around between the bit representing the first end time slot and the bit representing the second end time slot when representing the must-send time slot as chronologically after the could-send time slot.
Dependencies are inferred from the claim text.