External clock synchronization semiconductor memory device and method for controlling same
AssigneeNEC Electronics Corporation
InventorYoshisato Yokoyama
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Abstract
An external clock synchronization SRAM 1 of one embodiment comprises a SRAM cell, a global digit line, a global precharge circuit, a D latch, and a global precharge control circuit. A delay circuit is disposed in the global precharge control circuit so that the precharge output of the global precharge circuit changes with a delay with respect to the clock signal supplied to the D latch.
Claims19
An external clock synchronization semiconductor memory device in which each internal circuit operates according to a clock signal input from outside, comprising:
- a memory cell;
- a memory cell signal transmission line transmitting an output signal from the memory cell;
- a precharge circuit precharging the memory cell signal transmission line;
- a signal holding circuit fetching a signal transmitted by the memory cell signal transmission line according to a fetch control signal and outputting the fetched signal;
- and
- a precharge control circuit conducting control so that a precharge output of the precharge circuit changes with a delay with respect to the fetch control signal.
A control method for an external clock synchronization semiconductor memory device in which each internal circuit operates according to a clock signal input from outside, the control method comprising:
- selecting a memory cell for outputting a signal;
- fetching the selected memory cell output transmitted on a transmission line to a signal holding circuit and outputting the fetched signal as an output signal to the outside;
- and
- precharging the transmission line after the fetching of a signal by the signal holding circuit is prohibited.
Dependencies are inferred from the claim text.