High speed array pipeline architecture

A memory system, comprising:

• a memory controller;
• a memory device, said memory device comprising:
• a memory array having a plurality of memory cells;
• a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising:
• a first write driver connected to a first input/output line, said first input/output line being associated with a digitline connected to certain of said plurality of memory cells;
• a first read amplifier connected to said first input/output line;
• a first input/output device responsive to a first column select signal for connecting said first input/output line to said digitline;
• a second write driver connected to a second input/output line, said second input/output line being associated with said digitline;
• a second read amplifier connected to said second input/output line;
• and a second input/output device responsive to a second column select signal for connecting said second input/output line to said digitline;
• and a system bus interconnecting said memory controller and said memory device.

A computing system, comprising:

• a processor;
• an input device in communication with said processor for receiving data and instructions for operating said computing system;
• an output device in communication with said processor for displaying and outputting data generated by said processor;
• a data storage device in communication with said processor for storing software and data sets for use by said processor;
• and a memory system in communication with said processor, said memory system comprising:
• a memory controller;
• a memory device, said memory device comprising:
• a memory array having a plurality of memory cells;
• a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising:
• a first write driver connected to a first input/output line, said first input/output line being associated with a digitline connected to certain of said plurality of memory cells;
• a first read amplifier connected to said first input/output line;
• a first input/output device responsive to a first column select signal for connecting said first input/output line to said digitline;
• a second write driver connected to a second input/output line, said second input/output line being associated with said digitline;
• a second read amplifier connected to said second input/output line;
• and a second input/output device responsive to a second column select signal for connecting said second input/output line to said digitline;
• and a system bus interconnecting said memory controller and said memory device.