US 7,352,647 B1 · Reduced power usage in a memory for a programmable logic device

Abstract

A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data management circuit is used to programmably couple bitlines and/or wordlines to a selected number of memory sub-blocks necessary for respective read/write operations. During a respective read operation, the data management circuit uses row and/or column addresses to determine which memory bitlines and/or wordlines, and memory sub-blocks are essential in the read operation, leaving other non-essential bitlines and/or wordlines, and memory sub-blocks idle, thereby conserving power usage of the entire memory block. In one embodiment, a during respective read operation, a series of programmable pass-gates are used to selectively de-couple bitlines and/or wordlines, and memory sub-blocks that are not essential to the read operation.

Claims24

Dependent claims

A programmable logic device comprising:

a memory block having a plurality of memory sub-blocks;
a data control circuit that selectively connects charged read/write lines to one or more of the memory sub-blocks, wherein during a read operation the data control circuit connects charged read/write lines to only those memory sub-blocks necessary for the read operation,
wherein the data control circuit comprises a select line, wherein the select line causes the data control circuit to connect respective data read/write lines of at least two memory sub-blocks together in response to a signal indicative of connecting the data read/write lines, and wherein the signal comprises a most significant bit.

Dependencies are inferred from the claim text.

Reduced power usage in a memory for a programmable logic device

Life of this patent

Reduced power usage in a memory for a programmable logic device

Life of this patent

Abstract

Claims24