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US 7,352,646 B2Granted
Semiconductor memory device and method of arranging a decoupling capacitor thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHyung-Chan Choi, Chi-Wook Kim
Life of this patent
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Abstract
A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.
Claims18
A method of arranging a decoupling capacitor of a semiconductor memory device, the semiconductor memory device including a plurality of sub memory cell array blocks including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a plurality of local data I/O line pairs separately arranged between each of the plurality of the sub memory cell array blocks, and a plurality of global data I/O line pairs arranged in a perpendicular direction to the plurality of the local data I/O line pairs, the method comprising:
- arranging first sense amplifiers on left and right sides of each of first sub memory cell array blocks among the plurality of the sub memory cell array blocks;
- arranging second sense amplifiers, each having a different layout and construction from that of the first sense amplifiers, on left and right sides of each of second sub memory cell array blocks among the plurality of the sub memory cell array blocks with only the second of the first and second sub memory cell array blocks between the second sense amplifiers;
- and
- arranging the decoupling capacitor on an empty region of the plurality of the first and second sense amplifiers and connecting the decoupling capacitor between first and second power voltage lines;
- wherein of the first and second sense amplifiers, only the first sense amplifiers include local sense amplifiers.
2 more elements
A method of arranging a decoupling capacitor of a semiconductor memory device, the method comprising:
- arranging a plurality of first sense amplifiers on left and right sides of each of first sub memory cell array blocks among a plurality of sub memory cell array blocks;
- arranging a plurality of second sense amplifiers, each having a different layout and construction from that of the first sense amplifiers, on left and right sides of each of second sub memory cell array blocks among the plurality of sub memory cell array blocks with only the second of the first and second sub memory cell array blocks between the second sense amplifiers;
- and
- arranging the decoupling capacitor on an empty region of the plurality of first and second sense amplifiers and connecting the decoupling capacitor between a first and a second power voltage line;
- wherein of the first and second sense amplifiers, only the first sense amplifiers include local sense amplifiers.
2 more elements
A semiconductor memory device, comprising:
- a first group comprising
- first and second sub memory cell array blocks each including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;
- a first local data I/O line pair;
- a first global data I/O line pair arranged in a perpendicular direction to the first local data I/O line pair;
- a pair of first sense amplifiers arranged on opposing sides of the first sub memory cell array block;
- a pair of second sense amplifiers, electronically configured differently and having different construction than the first sense amplifiers, arranged on opposing sides of the second sub memory cell array block, wherein only the second of the first and second sub memory cell array blocks is between the second sense amplifiers,
- a second group comprising
- the first and second sub memory cell array blocks;
- a second local data I/O line pair operatively connected to the first and second sub memory cell array blocks;
- a second global data I/O line pair arranged in a perpendicular direction to the second local data I/O line pair;
- a second pair of the first sense amplifiers arranged on opposing sides of the first sub memory cell array block;
- and
- a second pair of the second sense amplifiers arranged on opposing sides of the second sub memory cell array block,
- wherein the first and the second local data I/O line pairs are electronically separate from each other, and
- wherein a decoupling capacitor is arranged on an empty region of the plurality of the first and second sense amplifiers and connected between first and second power voltage lines;
- wherein of the first and second sense amplifiers, only the first sence amplifers include local sense amplifiers.
13 more elements
A semiconductor memory device comprising:
- a plurality of groups of first and second sub memory cell array blocks including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the first and second sub memory cell array blocks alternately arranged;
- a plurality of local data I/O line pairs each separately connected to a different group of the first and second sub memory cell array blocks;
- a plurality of global data I/O line pairs arranged perpendicular to the plurality of local data I/O line pairs;
- a plurality of first sense amplifiers arranged on opposing sides of each of the groups of the first sub memory cell array blocks;
- and
- a plurality of second sense amplifiers arranged on opposing sides of each of the groups of the second sub memory cell array blocks, the first sense amplifier and the second sense amplifier having different layouts and constructions, wherein only the second of the first and second sub memory cell array blocks is between the second sense amplifiers,
- wherein a decoupling capacitor is arranged on an empty region of the plurality of first and second sense amplifiers and connected between first and second power voltage lines.
4 more elements
A semiconductor memory device, comprising:
- a plurality of first sense amplifiers;
- a plurality of first sub memory cell array blocks, each first sub memory cell array block disposed between a corresponding two of the first sense amplifiers;
- a plurality of second sense amplifiers;
- a plurality of second sub memory cell array blocks, each second sub memory cell array block disposed between a corresponding two of the second sense amplifiers;
- each first sense amplifier including:
- a plurality of bit line sense amplifiers coupled to a plurality of bit lines of the corresponding first sub memory cell array block;
- a plurality of data input/output gates, each data input/output gate coupled between a corresponding pair of the bit lines and a local data input/output line pair corresponding to the first sense amplifier;
- a local sense amplifier coupled between the local data input/output line pair and a global data input/output line pair;
- and
- a decoupling capacitor coupled between first and second power voltage lines for the first sense amplifier;
- and
- each second sense amplifier including:
- a plurality of bit line sense amplifiers coupled to a plurality of bit lines of the corresponding second sub memory cell array block;
- a plurality of data input/output gates, each data input/output gate coupled between a corresponding pair of the bit lines and a local data input/output line pair corresponding to the second sense amplifier;
- and
- a decoupling capacitor coupled between first and second power voltage lines for the second sense amplifier;
- wherein of the first and second sense amplifiers, only the first sense amplifiers include local sense amplifiers.
14 more elements
Dependencies are inferred from the claim text.