Memory device

A method, comprising:

• selecting at least one of a plurality of bit lines of a semiconductor memory device including a memory matrix including a plurality of memory cells arranged in a plurality of rows and a plurality of columns;
• and a bit line selection structure, the bit lines each being associated with a respective column of said plurality of columns, wherein the memory device includes a hierarchic column selecting structure that includes:
• a first hierarchic level comprising said bit lines;
• a levels hierarchy of levels higher than the first, said hierarchy comprising at least a level higher than the first, said level higher than the first comprising respective bit lines each associated with a respective packet of bit lines belonging to the lower hierarchic level, said packets of bit lines being grouped in a first and a second collection of packets, the packets belonging to the first collection being alternated with the packets belonging to the second collection;
• and
• clamping at a desired voltage at least a pair of bit lines, capacitively coupled to the at least one selected bit line, wherein the clamping includes clamping bit lines belonging to packets adjacent to the packet containing the selected bit line, wherein said bit lines in the adjacent packets result connected to the corresponding higher-level bit line as a result of the selection of the selected bit line, so as to automatically clamp the bit lines belonging to the level higher than the first adjacent to the bit line belonging to the level higher than the first corresponding to the packet which contains the selected bit line.

A semiconductor memory device, comprising:

• a plurality of memory cells arranged according to a plurality of rows and a plurality of columns;
• a plurality of global bit lines coupled to the columns;
• a bit line selector structured to select one of the bit lines;
• a plurality of clamping devices each coupled between a respective one of the bit lines and a reference voltage;
• a clamping controller structured to activate plural of the clamping devices that are coupled to non-selected bit lines adjacent to the selected bit line, thereby connecting the non-selected bit lines to the reference voltage;
• and
• a plurality of packets of local bit lines, each packet including a respective plurality of the local bit lines, each local bit line being associated with a respective column of the plurality of columns, and each global bit line being associated with a respective one of the packets of local bit lines.

A semiconductor memory device, comprising:

• a plurality of memory cells arranged according to a plurality of rows and a plurality of columns;
• a plurality of bit lines coupled to the columns;
• a bit line selector structured to select one of the bit lines;
• a plurality of clamping devices each coupled between a respective one of the bit lines and a reference voltage;
• and
• a clamping controller structured to activate plural of the clamping devices that are coupled to non-selected bit lines adjacent to the selected bit line, thereby connecting the non-selected bit lines to the reference voltage, wherein:
• the bit lines are grouped in at least first and second groups, the bit lines belonging to the first group being alternated with the bit lines belonging to the second group;
• the plurality of clamping devices is arranged according to two arrays, the bit lines belonging to the first group being connected to the clamping devices belonging to the first array, and the bit lines belonging to the second group being connected to the clamping devices belonging to the second array.

A semiconductor memory device, comprising:

• a plurality of memory cells arranged according to a plurality of rows and a plurality of columns;
• a plurality of bit lines coupled to the columns;
• a bit line selector structured to select one of the bit lines;
• a plurality of clamping devices each coupled between a respective one of the bit lines and a reference voltage;
• and
• a clamping controller structured to activate plural of the clamping devices that are coupled to non-selected bit lines adjacent to the selected bit line, thereby connecting the non-selected bit lines to the reference voltage, wherein the bit line selector includes a hierarchic column selecting structure comprising:
• a first hierarchic level comprising the plurality of bit lines;
• a hierarchy of levels higher than the first hierarchic level, the levels hierarchy comprising a level higher than the first hierarchic level, the level higher than the first hierarchic level comprising respective higher level bit lines each one associated with a respective packet of bit lines belonging to the lower hierarchic level;
• for each packet of bit lines, a respective plurality of selectors, each selector being coupled between a respective one of the bit lines and one of the higher level bit lines and having a control terminal;
• and
• a plurality of selecting signals that are activated in a mutually exclusive manner, each selection signal being coupled to the control terminal of a respective one of the selectors for each packet of bit lines.