Semiconductor memory with reset function

A memory comprising:

• an input buffer configured to generate a buffered reset signal RST from an external Reset signal;
• a first two-input NAND gate providing an internal reset signal Reset_En at its output and receiving the RST signal at a first input;
• a second two-input NAND gate having an output coupled to a second input of the first two-input NAND gate, the second two-input NAND gate having a first input coupled to the CKE signal through an inverting delay circuit;
• a two-input NOR gate receiving the RST signal at a first input and the CKE signal at a second input, the CKE signal indicating a time when the memory is ready to receive an external command;
• a pull-up transistor and a pull-down transistor serially coupled between a supply voltage and a ground potential, the pull-down transistor having a gate terminal coupled to an output of the two-input NOR gate;
• an inverter having its input coupled to a mode register programming signal MRSP and its output coupled to a gate terminal of the pull-up transistor, the MRSP signal indicating a time when a mode register in the memory is to be loaded with data;
• and
• a latch circuit coupled between a second input of the second two-input NAND gate and a node intermediate serially connected pull-up and pull-down transistors,
• wherein the Reset_En signal becomes active in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the memory are powered down.

A memory comprising:

• a first logic gate configured to receive an external Reset signal and generate an internal Reset_En signal, the first logic gate causing the Reset_En signal to become active in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the memory are powered down;
• a second logic gate being configured to receive an external clock enable signal CKE, an output terminal of the second logic gate being coupled to an input terminal of the first logic gate, wherein a duration of the internal reset interval is at least in part dependent on when the CKE signal becomes active to indicate that the memory is ready to receive an external command;
• and
• a latch circuit coupled between a biasing circuit and an input terminal of the second logic gate, the biasing circuit being configured to bias the latch circuit in a first state in order to maintain the Reset_En signal in active state when both the external Reset signal and the CKE signal are in inactive state.

A method of resetting a memory, the method comprising:

• causing an internal reset signal Reset_En to become active when an external Reset signal becomes active, thereby starting an internal reset interval during which one or more circuit blocks in the memory are powered down;
• terminating the internal reset interval when an external clock enable signal CKE becomes active indicating that the memory is ready to receive an external command;
• and
• biasing a latch circuit in a first state in order to maintain the Reset_En signal in active state during a time when both the external Reset signal and the CKE signal are in inactive state.