Regulating voltages for refresh operation using flash trim bits in semiconductor memory devices
AssigneeMicron Technology, Inc.
InventorsTheodore T. Pekny, Stephen J. Gualandri
Life of this patent
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Abstract
A method and apparatus for regulating voltages in semiconductor devices. Trim bits are stored in a trim flash array, where the trim bits define a voltage value and where the voltage value is accessible once a control signal representing a word line signal is provided to the trim flash array reaches a selected voltage level. A refresh signal is provided to a voltage regulator in response to the control signal reaching the selected level, causing the voltage regulator to change its regulation value to that defined by the trim bits. A signal at a voltage level represented by the voltage value is provided to a memory array that is accessed based on the provided signal.
Claims11
A method, comprising:
- storing trim bits in a trim flash array, where the trim bits define a voltage value and where the voltage value is accessible once a control signal provided to the trim flash array reaches a selected voltage level, wherein the control signal represents a word line signal;
- providing a refresh signal to a voltage regulator in response to the control signal reaching the selected level, causing the voltage regulator to change its regulation value to that defined by the trim bits;
- providing, using the voltage regulator, a signal at a voltage level represented by the voltage value to a memory array;
- and
- accessing the memory array based on the provided signal.
A memory, comprising:
- a memory cell array;
- a trim flash array adapted to provide a voltage regulation value in response to receiving a word line signal;
- a refresh circuit communicatively coupled to the trim flash array, comprising:
- an inverter adapted to invert the word line signal;
- and
- a delay element adapted to delay the inverted word line signal by a selected time interval;
- a gate adapted to provide a refresh signal based on at least one of the word line signal and the delayed inverted word line signal;
- a voltage regulator communicatively coupled to the trim flash array and the refresh circuit, wherein the voltage regulator is adapted to provide a signal of a voltage level that is indicated by the voltage regulation value to the memory cell array based on the refresh signal.
A system, comprising:
- a device;
- and
- a memory that is accessible by the device, wherein the memory comprises:
- a memory cell array;
- a trim flash array adapted to provide a voltage regulation value in response to receiving a word line signal;
- a refresh circuit communicatively coupled to the trim flash array, comprising:
- an inverter adapted to invert the word line signal;
- and
- a delay element adapted to delay the inverted word line signal by a selected time interval;
- a gate adapted to provide a refresh signal based on at least one of the word line signal and the delayed inverted word line signal;
- a voltage regulator communicatively coupled to the trim flash array and the refresh circuit, wherein the voltage regulator is adapted to provide a signal of a voltage level that is indicated by the voltage regulation value to the memory cell array based on the refresh signal.
Dependencies are inferred from the claim text.