Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• and
• wherein
• the refresh operation is executed during a precharge period between the read or write operation and a next read or write operation.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outpuffing an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• a first flip-flop circuit latching a refresh request signal based on an output signal from the refresh request circuit;
• and
• a second flip-flop circuit outputting a refresh signal for starting the refresh operation based on the refresh request signal during a precharge period between the read or write operation and a next read or write operation.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• and
• wherein
• while the refresh operation is executed, a busy signal based on the refresh signal is output to an outside of the semiconductor memory device.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• a first local bit line connected to the memory cells;
• a first main bit line provided to correspond to a plurality of the first local bit lines;
• a data sense amplifier provided to correspond to the first main bit line and detecting data of the memory cell;
• a first switching circuit connected between the first main bit line and the first local bit line;
• a second local bit line connected to the counter cell;
• a second main bit line provided to correspond to a plurality of the second local bit lines;
• a counter sense amplifier provided to correspond to the second main bit line and detects the data of the counter cell;
• and
• a second switching circuit connected between the second main bit line and the second local bit line.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh reciuest circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• and
• wherein
• data on the number of times of activation is divided into data elements each consisting of one bit or a plurality of bits, and the divided data elements are stored in a plurality of the counter cells belonging to the counter cell arrays.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• and
• wherein
• after a power of the semiconductor memory device is turned on, the refresh operation is executed to the counter cell so as to initialize the counter cell.

A semiconductor memory device comprising:

• a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region;
• a memory cell array including a plurality of the memory cells;
• word lines connected to the memory cells arranged in rows of the memory cell array;
• a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines;
• an adder incrementing the number of times of activation of one of the word lines, the number of times of activation beina read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell;
• a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array;
• a refresh request circuit outputtina an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value;
• and
• wherein
• after a power of the semiconductor memory device is turned on, the counter cell is set into a standby state during a period equal to or longer than a data retention period of the counter cell, and the data of all of a plurality of the counter cells are logically made equal.