Dynamic memory throttling for power and thermal limitations
AssigneeSun Microsystems, Inc.
InventorChung-Hsiao R. Wu
Life of this patent
Estimating the term…
Abstract
In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the sensed temperature. In a further embodiment, a sensor is positioned to detect a power condition associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the detected power condition.
Claims8
An apparatus comprising:
- a memory subsystem;
- a memory controller coupled to said memory subsystem and configured to control accesses to said memory subsystem;
- and
- a sensor coupled to detect a power condition associated with said memory subsystem;
- wherein said memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon said detected power condition;
- wherein said detected power condition is a current draw associated with said memory subsystem.
A method comprising:
- detecting a power condition associated with a memory subsystem;
- and
- selectively inserting one or more idle clock cycles between a first memory access and a second memory access depending upon said detected power condition;
- wherein said detected power condition is a current draw associated with said memory subsystem, wherein in response to said detected current draw being greater than a predetermined threshold, the method further comprises inserting said one or more idle clock cycles between a plurality of memory accesses at a particular rate.
A computer system comprising:
- a processor;
- a memory subsystem;
- a memory controller coupled to said processor and said memory subsystem, wherein said memory controller is configured to control accesses to said memory subsystem by said processor;
- a sensor coupled to detect a current draw associated with said memory subsystem;
- and
- a service processor coupled to said memory controller, wherein in response to said detected current draw being greater than a predetermined threshold, said service processor is configured to program said memory controller to insert one or more idle clock cycles between a first memory access and a second memory access.
Dependencies are inferred from the claim text.