Method and apparatus for testing a memory device
AssigneeSpansion LLC
InventorsKatsutoshi Suitou, Yoshichika Nakaya
Life of this patent
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Abstract
The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a defective sector), the compulsory signal FMATCH is brought to a HIGH level. The match signal MATCH is forcedly brought to a HIGH level (S22) in compliance with the compulsory signal FMATCH which is at a HIGH level (S21:T). And, verification (S2a) is skipped for the defective sectors, whereby the address signal for identifying the ordinary memory blocks may be utilized for identification of redundant memory blocks.
Claims16
A method for testing a memory device that includes an ordinary memory block and a redundant memory block and conducts a test by using a built-in self-testing function, the method comprising the steps of:
- generating an address signal for identifying the ordinary memory block and contents thereof;
- identifying the ordinary memory block and contents thereof in response to the address signal during the test of the ordinary memory block;
- outputting a test target control signal for selecting the redundant memory block as the test target in response to the address signal transiting from an address which identifies a last test target in the ordinary memory block;
- selecting the redundant memory block as a test target in the test by the built-in self-testing function in response to the test target control signal;
- and
- identifying the redundant memory block and contents thereof in accordance with the address signal after the step of selecting the redundant memory block as the test target.
A method for testing a memory device that includes an ordinary memory block and a redundant memory block and conducts a test by using a built-in self-testing function, the method comprising the steps of:
- generating an address signal for identifying the ordinary memory block and contents thereof;
- outputting a test target control signal;
- selecting the redundant memory block as a test target in the test by the built-in self-testing function in response to the test target control signal;
- identifying the redundant memory block and contents thereof in accordance with the address signal;
- outputting the test target control signal for selecting the ordinary memory block as the test target in response to the address signal transiting from an address which identifies a last test target in the redundant memory block;
- and
- identifying the ordinary memory block and contents thereof in response to the address signal during the test of the ordinary memory block.
A memory device that includes an ordinary memory block and a redundant memory block and conducts a test by using a built-in self-testing function, the memory device comprising:
- an address sequencer which generates an address signal for identifying the ordinary memory block and contents thereof;
- and
- a test target control section which outputs a test target control signal for substituting identification of the redundant memory block and contents thereof for the address signal during the test of the redundant memory block, the test target control section outputting the test target control signal in response to the address signal transiting from a last address signal in the ordinary memory block by the address sequencer in the case where the test of the redundant memory block is conducted following the test of the ordinary memory block.
Dependencies are inferred from the claim text.