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US 7,352,633 B2Granted
Multibit memory cell
AssigneeIntel Corporation
InventorJohn R. Cherukuri
Life of this patent
Estimating the term…
Abstract
Provided are a method, system and device for storing multiple bits into a multibit memory cell. In the illustrated embodiment, each multibit memory cell is a “quadbit” cell capable of storing 4 bits which are read out on four bit lines of the cell in response to activation of a common word line. In the illustrated embodiment, the bit subcells of each cell are arranged in a 2 by 2 array in which two pairs of subcells are each aligned in a longitudinal direction . Conversely, each of two pairs of subcells are also aligned in a transverse direction. Additional embodiments are described and claimed.
Claims20
A memory, comprising:
- a cell having a plurality of bit subcells, each bit subcell being adapted to store a bit of a common word, wherein said bit subcells are arranged in an array within said cell, said array having a plurality of bit subcells in a longitudinal direction and a plurality of bit subcells in a transverse direction;
- wherein said longitudinal and transverse directions are orthogonal, said cell has four bit subcells, wherein said array is a 2 by 2 array of bit subcells within said cell, said cell has a word line electrically coupled to each subcell, each subcell has a bit line output and at least one subcell has a transistor having a control input electrically coupled to a word line and an output electrically coupled an associated bit line output of said at least one bit subcell, and said word line comprises a conductive metal strapping line positioned across said cell, and a pair of semiconductor lines, each semiconductor line being positioned across a pair of bit subcells of said 2 by 2 array of bit subcells and electrically coupled to a control input of a transistor if present within a bit subcell of said pair of bit subcells, each semiconductor line further being electrically coupled to said strapping line.
A processor, comprising:
- controller logic;
- and
- a memory coupled to said logic and including a plurality of cells, each cell having a plurality of bit subcells, each bit subcell being adapted to store a bit of a common word, wherein said bit subcells are arranged in an array within said cell, said array having a plurality of bit subcells in a longitudinal direction and a plurality of bit subcells in a transverse direction;
- wherein said longitudinal and transverse directions are orthogonal and wherein said cell has four bit subcells, wherein said array is a 2 by 2 array of bit subcells within said cell, said cell has a word line electrically coupled to each subcell, each subcell has a bit line output and at least one subcell has a transistor having a control input electrically coupled to a word line and an output electrically coupled an associated bit line output of said at least one bit subcell, and said word line comprises a conductive metal strapping line positioned across said cell, and a pair of semiconductor lines, each semiconductor line being positioned across a pair of bit subcells of said 2 by 2 array of bit subcells and electrically coupled to a control input of a transistor if present within a bit subcell of said pair of bit subcells, each semiconductor line further being electrically coupled to said strapping line.
1 more element
A system, comprising
- a processor;
- a read only memory coupled to said processor and including a plurality of cells, each cell having a plurality of bit subcells, each bit subcell being adapted to store a bit of a common word, wherein said bit subcells are arranged in an array within said cell, said array having a plurality of bit subcells in a longitudinal direction and a plurality of bit subcells in a transverse direction;
- and
- a video controller;
- wherein said longitudinal and transverse directions are orthogonal and wherein said cell has four bit subcells, wherein said array is a 2 by 2 array of bit subcells within said cell, said cell has a word line electrically coupled to each subcell, each subcell has a bit line output and at least one subcell has a transistor having a control input electrically coupled to a word line and an output electrically coupled an associated bit line output of said at least one bit subcell, and said word line comprises a conductive metal strapping line positioned across said cell, and a pair of semiconductor lines, each semiconductor line being positioned across a pair of bit subcells of said 2 by 2 array of bit subcells and electrically coupled to a control input of a transistor if present within a bit subcell of said pair of bit subcells, each semiconductor line further being electrically coupled to said strapping line.
2 more elements
A method, comprising:
- selecting a common word line electrically coupled to each of four bit subcells of a cell of a read only memory, wherein said bit subcells are arranged in a 2 by 2 array within said cell;
- and
- reading four bit lines of said cell, each bit line being electrically coupled to an output of an associated bit subcell of said cell;
- wherein logical bits have been selectively programmed into said four bit subcells of a cell of a read only memory, in which a transistor has been one of placed and omitted in a bit subcell in accordance with the value of the programmed logical bit.
1 more element
A method, comprising:
- selectively programming logical bits into four bit subcells of a cell of a read only memory, wherein said bit subcells are arranged in a 2 by 2 array within said cell and have a common word line and wherein said logical bit selective programming includes one of placing and omitting placing a transistor in a bit subcell in accordance with the value of the logical bit being programmed.
Dependencies are inferred from the claim text.