Semiconductor memory device and memory card

A semiconductor memory device, comprising:

• a plurality of word lines which are provided along a first direction gate electrodes of memory cells being respectively connected to the word lines;
• a first select gate line which is provided along the first direction, a gate electrode of a first select transistor being connected to the first select gate line;
• a second select gate line which is provided along the first direction, a gate electrode of a second select transistor being connected to the second select gate line, and the second select gate line being located across the first select gate line from a first adjacent word line which is a word line adjacent to the first select gate line;
• a third select gate line which is provided along the first direction, a gate electrode of a third select transistor being connected to the third select gate line, and the third select gate line being adjacent to a second adjacent word line which is a word line located on a side opposite to the first adjacent word line;
• and
• a fourth select gate line which is provided adjacent to the third select gate line along the first direction, a gate electrode of a fourth select transistor being connected to the fourth select gate line, and the fourth select gate line being located across the third select gate line from the second adjacent word line,
• wherein when data in a memory cell is read, the voltage of the first select gate line is increased after voltages of the third select gate line and the fourth select gate line are increased, and thereafter the voltage of the second select gate line is increased, and
• the semiconductor memory device further comprises a bit line which is connected to the fourth select transistor,
• wherein a voltage of the bit line is increased after the voltages of the third select gate line and the fourth select gate line are increased and before the voltages of the word lines are increased, when data in a memory cell connected to the first adjacent word line is read, and
• wherein the voltage of the bit line is increased after the voltages of the first select gate line and the second select gate line are increased and before the voltages of the word lines are increased, when data in a memory cell connected to the second adjacent word line is read.

A memory card including a semiconductor memory device, wherein the semiconductor memory device comprises:

• a first select gate line which is provided along a first direction, a gate electrode of a first select transistor being connected to the first select gate;
• a second select gate line which is provided along the first direction, a gate electrode of a second select transistor being connected to second select gate;
• and
• a plurality of word lines which are provided between the first select gate line and the second select gate line along the first direction, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is a word line adjacent to the first select gate line is read, voltages of the word lines are increased after a voltage of the first select gate line is increased and a voltage of the second select word line is increased after the voltages of the word lines are increased, and when data in a memory cell connected to a second adjacent word line which is a word line adjacent to the second select gate line is read, voltages of the word lines are increased after the voltage of the second gate line is increased and a voltage of the first select word line is increased after the voltages of the word lines are increased.

A memory card including a semiconductor memory device, wherein the semiconductor memory device comprises:

• a plurality of word lines which are provided along a first direction, gate electrodes of memory cells being respectively connected to the word lines;
• a first select gate line which is provided along the first direction, a gate electrode of a first select transistor being connected to the first select gate line;
• a second select gate line which is provided along the first direction, a gate electrode of a second select transistor being connected to the second select gate line, and the second select gate line is located across the first select gate line from a first adjacent select gate line which is a word line adjacent to the first select gate line;
• a third select gate line which is provided along the first direction, a gate electrode of a third select transistor being connected to the third select gate line, and the third select gate line being adjacent to a second adjacent word line which is a word line located on a side opposite to the first adjacent word line;
• and
• a fourth select gate line which is provided adjacent to the third select gate line along the first direction, a gate electrode of a fourth select transistor being connected to the fourth select gate line, and the fourth select gate line being located across the third select gate line from the second adjacent word line,
• wherein when data in a memory cell is read, the voltage of the first select gate line is increased after voltages of the third select gate line and the fourth select gate line are increased, and thereafter the voltage of the second select gate line is increased, and
• the semiconductor memory device further comprises a bit line which is connected to the fourth select transistor,
• wherein a voltage of the bit line is increased after the voltages of the third select gate line and the fourth select gate line are increased and before the voltages of the word lines are increased, when data in a memory cell connected to the first adjacent word line is read, and
• wherein the voltage of the bit line is increased after the voltages of the first select gate line and the second select gate line are increased and before the voltages of the word lines are increased, when data in a memory cell connected to the second adjacent word line is read.