Reduction of adjacent floating gate data pattern sensitivity
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.
Claims20
A method for programming an array of memory cells arranged in rows and columns in a system having a capacitive coupling effect between adjacent memory cells, each memory cell having a first threshold voltage distribution window and a first programming step voltage that do not take into account the capacitive coupling effect, the method comprising:
- generating programming pulses to a first memory cell such that a coupling effect from adjacent memory cells is taken into account, the programming pulses comprising a series of programming voltages, each programming voltage in the series increased by a second programming step voltage from a previous programming voltage such that the first memory cell is in a second threshold voltage distribution window determined in response to the capacitive coupling effect, the second programming step voltage greater than the first programming step voltage and the second threshold voltage distribution window greater than the first threshold voltage distribution window.
A method for programming an array of memory cells arranged in rows and columns in a system having a capacitive coupling effect between adjacent memory cells, each memory cell having a first threshold voltage distribution window and a first programming step voltage that do not take into account the capacitive coupling effect, the method comprising:
- generating a second programming step voltage that takes into account the capacitive coupling effect, the second programming step voltage greater than the first programming step voltage;
- and
- generating a second threshold voltage distribution window that takes into account the capacitive coupling effect, the second threshold voltage distribution window wider than the first threshold voltage distribution window.
A method for programming an array of memory cells arranged in rows and columns, the method comprising:
- generating programming pulses to a first memory cell to program the first memory cell to a first threshold voltage such that a coupling effect from adjacent memory cells is taken into account;
- verifying that the first memory cell is programmed to the first threshold voltage;
- generating programming pulses to a second memory cell adjacent the first memory cell;
- and
- after generating the programming pulses to the second memory cell, performing a verification operation to determine whether the first memory cell is programmed to a second threshold voltage greater than the first threshold voltage.
Dependencies are inferred from the claim text.