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US 7,352,623 B2Granted
NOR flash memory device with multi level cell and read method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsBo-Geun Kim, Heung-Soo Lim, Jae-Woo Lim
Life of this patent
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Abstract
A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell.
Claims23
A NOR flash memory device comprising:
- a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage;
- a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell, the discharge circuit including:
- an inverter responsive to a latch control signal;
- and
- a transistor coupled to the bit line and a ground and responsive to the output of the inverter;
- and
- a data latch circuit configured to enable the discharge circuit when the multi level memory cell is sensed as the on cell.
4 more elements
A method of reading a NOR flash memory device comprising:
- sensing a multi level memory cell coupled to a bit line in response to a first of a plurality of word line voltages;
- discharging the bit line if the multi level memory cell is sensed as a first state;
- and
- continuing sensing the multi level memory cell if the multi level memory cell is sensed in a second state, including:
- sensing the multi level memory cell in response to a second word line voltage;
- discharging the bit line if the multi level memory cell is sensed as the first state;
- and
- continuing sensing the multi level memory cell if the multi level memory cell is sensed in the second state.
5 more elements
A NOR flash memory device comprising:
- a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage;
- a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell;
- and
- a precharge circuit coupled to the bit line and a power supply, and configured to precharge the bit line and to discontinue precharging when the multi level memory cell is sensed as an on cell, the precharge circuit including:
- a NAND gate responsive to a bit line precharge signal and a latch control signal;
- and
- a transistor coupled to the power supply and the bit line and responsive to the output of the NAND gate.
4 more elements
A method of reading a NOR flash memory device comprising:
- sensing a multi level memory cell coupled to a bit line in response to a first of a plurality of word line voltages;
- discharging the bit line if the multi level memory cell is sensed as a first state;
- and
- continuing sensing the multi level memory cell if the multi level memory cell is sensed in a second state including:
- sensing the multi level memory cell in response to each of the other word line voltages;
- and
- discharging the bit line if the multi level memory cell is sensed as the first state through subsequent sensings using subsequent word line voltages.
4 more elements
Dependencies are inferred from the claim text.