Multi-level cell memory device and associated read method
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Han Kim, Seung-Keun Lee
Life of this patent
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Abstract
A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.
Claims38
A NOR flash memory device, comprising:
- a memory cell adapted to store two or more bits of data;
- a reference voltage generator adapted to generate a plurality of different reference voltages;
- a sense amplifier adapted to sequentially detect the values of the two or more bits of data according to a reference current whose magnitude is determined by the different reference voltages;
- and
- a selection circuit adapted to select which of the different reference voltages determine the magnitude of the reference current.
A NOR flash memory device, comprising:
- a memory cell adapted to store two or more bits of data;
- a reference voltage generator adapted to generate a plurality of different reference voltages;
- a sense amplifier adapted to sequentially detect the values of the two or more bits of data according to a reference current whose magnitude is determined by the different reference voltages;
- a latch circuit adapted to store the values detected by the sense amplifier;
- and
- a selection circuit adapted to select which of the different reference voltages determine the magnitude of the reference current.
A NOR flash memory device comprising:
- a memory cell adapted to store two or more bits of data;
- a reference voltage generator adapted to generate a plurality of different reference voltages;
- a sense amplifier adapted to sequentially detect the values of the two or more bits of data according to a reference current whose magnitude is determined by the different reference voltages;
- a latch circuit adapted to store the values detected by the sense amplifier;
- and
- a selection circuit adapted to select which of the different reference voltages determine the magnitude of the reference current;
- and
- a switch circuit adapted to provide one of the different reference voltages to the sense amplifier in response to a plurality of selection signals generated by the selection circuit.
A method of sequentially detecting the values of two or more bits of data stored in a memory cell of a NOR flash memory device, the method comprising:
- detecting the value of a most significant bit of data stored in the memory cell according to a voltage level apparent at a sensing node;
- upon detecting the value of the most significant bit, precharging the sensing node to a predetermined voltage level;
- and,
- sensing the value of a least significant bit stored in the memory cell according to the value of the most significant bit;
- wherein the value of the most significant bit is detected in response to a most significant bit enable signal ENMSB.
A flash memory device, comprising:
- a memory cell adapted to store two or more bits of data;
- a reference voltage generator adapted to generate a plurality of different reference voltages;
- a sense amplifier adapted to sequentially detect the values of the two or more bits of data according to a reference current whose magnitude is determined by the different reference voltages;
- and
- a selection circuit adapted to select which of the different reference voltages determine the magnitude of the reference current.
A NOR flash memory device, comprising:
- a memory cell adapted to store two or more bits of data;
- a sense amplifier adapted to sequentially detect the values of the two or more bits of data according to a reference circuit;
- and
- a sensing node precharge circuit adapted to precharge a sensing node to a predetermined voltage level after the sense amplifier detects one bit among the two or more bits of data.
Dependencies are inferred from the claim text.