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US 7,352,617 B2Granted
Nano tube cell and memory device using the same
AssigneeHynix Semiconductor Inc.
InventorHee Bok Kang
Life of this patent
Estimating the term…
Abstract
A nano tube cell and a memory device using the same features a cross point cell using a capacitor and a PNPN nano tube switch to reduce the whole memory size. In the memory device, the unit nano tube cell comprising a capacitor and a PNPN nano tube switch which does not an additional gate control signal is located where a word line and a bit line are crossed, so that a cross point cell array is embodied. As a result, the whole chip size is reduced, and read and write operations are effectively improved.
Claims18
A nano tube cell comprising:
- a capacitor whose one terminal is connected to a word line;
- and
- a PNPN nano tube switch, which includes a first PNPN diode switch connected forward between a bit line and a bottom electrode of the capacitor, and a second PNPN diode switch connected backward between the bit line and the bottom electrode of the capacitor successively connected in series and divided into two groups each connected in parallel between the bit line and the other terminal of the capacitor, for being selectively switched depending on a voltage applied to the word line and the bit line,
- wherein the PNPN nano tube switch is switched to read data stored in the capacitor when a first voltage is applied to the word line, and to write data in the capacitor when a second voltage larger than the first voltage is applied to the bit line,
- wherein the first PNPN diode switch has an upper P-type region connected to the bottom electrode and a lower N-type region connected to the bit line.
2 more elements
A nano tube cell comprising:
- a PNPN nano tube switch including an insulating layer formed on a substrate and at least two or more PNPN diode switches which are made of silicon layers on the insulating layer and successively connected in series;
- a capacitor, which comprises a top electrode, an insulating film and a bottom electrode, for reading and writing data depending on the amount of current applied from a word line or a bit line;
- a bit line connected to both nodes of the PNPN nano tube switches through a bit line contact node;
- a contact node for connecting the bottom electrode to a common node where at least two or more PNPN diode switches are connected;
- and
- a word line formed on the top electrode.
3 more elements
A memory device using a nano tube cell, comprising:
- a plurality of nano tube cell arrays each including a plurality of unit nano tube cells arranged in row and column directions;
- a plurality of word line driving units for selectively driving word lines of the plurality of nano tube cell arrays;
- and
- a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of nano tube cell arrays,
- wherein each of the plurality of unit nano tube cells comprises:
- a capacitor whose one terminal is connected to a word line;
- and
- a PNPN nano tube switch, which includes at least two or more PNPN diode devices successively connected in series and divided into two groups each connected in parallel between a bit line and the other terminal of the capacitor, for being selectively switched depending on a voltage applied to the word line and the bit line.
5 more elements
Dependencies are inferred from the claim text.