US 7,352,610 B1 · Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits

Abstract

Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

Claims15

Dependent claims

An integrated circuit memory element with immunity to soft error upset events, comprising:

first and second cross-coupled inverters each having an input and an output and each having two transistors with gates;
and
at least one nonlinear high-impedance two-terminal element having a first terminal connected to the output of the second inverter and a second terminal connected to at least one of the gates of the first inverter, wherein the nonlinear high-impedance two-terminal element comprises a p-n junction diode having doped n-type polysilicon and doped p-type polysilicon.

A programmable logic device integrated circuit containing programmable logic that is configured by loading configuration data into the programmable logic device integrated circuit, comprising:

an array of memory elements each of which includes at least one nonlinear high-impedance two-terminal element that provides the memory element with immunity to soft error upset events, wherein the array of memory elements is arranged in a plurality of banks;
a plurality of sets of latches each associated with a respective one of the plurality of banks of memory elements, wherein each set of latches loads configuration data into its respective bank of memory elements;
and
circuitry that receives the configuration data for configuring the programmable logic and that provides the configuration data to the sets of latches, wherein at least some of the sets of latches load their respective banks of memory elements at the same time.

1 more element

Dependencies are inferred from the claim text.

Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits

Life of this patent

Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits

Life of this patent

Abstract

Claims15