Nonvolatile ferroelectric memory device and method thereof

A nonvolatile ferroelectric memory device having at least one ferroelectric memory cell array, the ferroelectric memory cell array comprising:

• a plurality of top word lines;
• a plurality of bottom word lines;
• a plurality of selection lines;
• a plurality of sense lines;
• a plurality of bit lines;
• a plurality of sense amplifiers respectively connected to the plurality of bit lines;
• and
• a plurality of ferroelectric memory cells connected to the top word lines, the bottom word lines, the selection lines, the sense lines, and the bit lines,
• wherein each of the plurality of ferroelectric memory cells comprises:
• a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell;
• and
• a second double gate cell selectively turned on by a potential on a corresponding one of the selection lines to selectively supply a potential of a corresponding one of the sense lines to the first double gate cell so as to control read and write operations of the first double gate cell.

A nonvolatile ferroelectric memory device having at least one ferroelectric memory cell array, the ferroelectric memory cell array comprising:

• a plurality of top word lines;
• a plurality of bottom word lines;
• a plurality of selection lines;
• a plurality of sense lines;
• a plurality of bit lines;
• a plurality of sense amplifiers respectively connected to the plurality of bit lines;
• and
• a plurality of ferroelectric memory cells connected to the top word lines, the bottom word lines, the selection lines, the sense lines, and the bit lines,
• wherein each of the plurality of ferroelectric memory cells comprises:
• a double gate cell for storing a bit of datum, the double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell;
• and
• a switch unit selectively turned on by a potential on a corresponding one of the selection lines to selectively supply a potential of a corresponding one of the sense lines to the double gate cell so as to control read and write operations of the double gate cell.

A method for operating a nonvolatile ferroelectric memory device having a plurality of ferroelectric memory cells arranged in a plurality of rows and columns, each row corresponding to one of a plurality of top word lines, one of a plurality of bottom word lines, one of a plurality of selection lines, and one of a plurality of sense lines, and each column corresponding to one of a plurality of bit lines, wherein each of the plurality of ferroelectric memory cells comprises a double gate cell for storing a bit of datum and a switch unit selectively turned on by a potential on a corresponding one of the selection lines to supply a potential on a corresponding one of the sense lines to the double gate cell to control read and write operations of the double gate cell, the method comprising:

• writing a bit of “1” into each of first ones of the ferroelectric memory cells by
• applying a positive voltage to the corresponding selection line to turn off the corresponding switch unit,
• applying a ground voltage to the corresponding bit line and the corresponding bottom word line, and
• applying a negative polarization transition threshold voltage to the corresponding top word line.