US 7,352,604 B2 · Memory and driving method of the same

Abstract

According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

Claims62

Dependent claims

A memory comprising:

a memory cell;
a clocked inverter including at least a transistor;
and
a column decoder,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line, and
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder.

6 more elements

A memory comprising:

a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder;
and
a Read/Write circuit including a second switch, a third switch, a first logic circuit and a second logic circuit,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to an output node of the first logic circuit,
a gate electrode of a third transistor included in the third switch is electrically connected to an output node of the second logic circuit,
a first input node of the first logic circuit is electrically connected to a Read Enable signal line,
a second output node of the first logic circuit is electrically connected to a Chip Enable signal line,
a first input node of the second logic circuit is electrically connected to a Write Enable signal line, and
a second input node of the second logic circuit is electrically connected to a Chip Enable signal line.

15 more elements

A memory comprising:

a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder;
and
a Read/Write circuit including a second switch, a third switch, a first logic circuit and a second logic circuit,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter, an output node of the clocked inverter is electrically connected to a data line
through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to an output node of the first logic circuit,
a gate electrode of a third transistor included in the third switch is electrically connected to an output node of the second logic circuit,
a first input node of the first logic circuit is electrically connected to a Read Enable signal line,
a second output node of the first logic circuit is electrically connected to a Chip Enable signal line,
a first input node of the second logic circuit is electrically connected to a Write Enable signal line,
a second input node of the second logic circuit is electrically connected to a Chip Enable signal line, and
the memory cell includes a transistor having two gates, one of the two gates is a floating gate.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/607,053Filed 1 Dec 2006 · continuation

Priority

JP 2003-29181111 Aug 2003

Published

US 2007/0076515 A15 Apr 2007

Granted

1 Apr 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/1096
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: write circuits, e.g.…
G11C 7/1078
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits

Family

Application10/890,173Parent of this continuation · filed 14 Jul 2004

US 2007/0076515 A1Pre-grant publication · published 5 Apr 2007

US 7,158,439 B2Parent of this continuation

US 2005/0047266 A1Published application

US 7,352,604 B2This patent

From the US filing history. Foreign family members aren’t listed.

Memory and driving method of the same

Life of this patent

Memory and driving method of the same

Life of this patent

Abstract

Claims62