Analog-to-digital converter with non-linearity compensation

A method for converting an analog input value to an output digital code, the method comprising:

• at a first analog-to-digital converter (ADC), receiving the analog input value and converting the analog input value to a first digital code;
• at a first digital-to-analog converter (DAC), converting the first digital code to a first analog value;
• at a first linearization module, receiving the first digital code and producing a first linear-correction correction code;
• at a second ADC, receiving a remainder portion of the analog input value and converting the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;
• wherein a full-scale range of the second ADC is at least as large as the remainder portion, and wherein the remainder portion includes a quantization error contributed from the first ADC and non-linearity errors contributed from the first ADC, from the first DAC, and from a subtractor that computes the remainder portion, the first linear-correction code directly compensating for non-linearity errors contributed from the first DAC and from the subtractor;
• at a second linearization module, receiving the second digital code and producing a second linear-correction code;
• and
• combining the first linear-correction code and the second linear-correction code to produce the output digital code.

An analog-to-digital converter (ADC) for converting an analog input value to an output digital code, the ADC comprising:

• a first ADC configured to receive the analog input value and to convert the analog input value to a first digital code;
• a digital-to-analog converter (DAC) coupled to the output of the first ADC and configured to convert the first digital code to a first analog value;
• a first two-dimensional lookup table coupled to the output of the first ADC and configured to receive the first digital code and to store first and second linear-correction codes that are approximately equal to first and second analog output voltage values measured previously for the DAC in response to the first two-dimensional lookup table receiving the first digital code, wherein the first two-dimensional lookup table is configured to:
• compare the first digital code to a previous code produced by the first ADC;
• select the first linear-correction code if the first digital code is larger than the previous code;
• and
• select the second linear-correction code if the first digital code is less than the previous code;
• a subtractor coupled to the output of the DAC and configured to subtract the first analog value from the analog input value to produce a remainder value;
• a second ADC coupled to the output of the subtractor and configured to convert the remainder value to a second digital code;
• a second two-dimensional lookup table coupled to the ouput of the second ADC and configured to receive the second digital code and to store third and fourth linear-correction codes that are approximately equal to third and fourth analog input voltage values measured previously for the second digital code, wherein the second two-dimensional lookup table is configured to:
• compare the second digital code to a previous code produced by the second ADC;
• select the third linear-correction code if the second digital code is larger than the previous code;
• and
• select the fourth linear-correction code if the second digital code is less than the previous code;
• and
• an accumulator configured to combine one of the first and second linear-correction codes and one of the third and fourth linear-correction codes to produce the output digital code.

An analog-to-digital converter (ADC) for converting an analog input value to an output digital code, the ADC comprising:

• a first analog-to-digital converter configured to receive the analog input value and to convert the analog input value to a first digital code;
• a first digital-to-analog converter (DAC) configured to convert the first digital code to a first analog value;
• a first linearization module configured to receive the first digital code and to produce a first linear-correction code that is approximately equal to the first analog value, wherein the first linearization module stores linear-correction codes previously determined by measuring output values produced by the first DAC in response to receiving multiple digital input values, the linear-correction codes including the first linear-correction code;
• a second ADC configured to receive a remainder portion of the analog input value and to convert the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;
• a second linearization module configured to receive the second digital code and to produce a second linear-correction code;
• and
• an accumulator configured to combine the first linear-correction code and the second linear-correction code to produce the output digital code.

A method for converting an analog input value to a multi-stage analog-to-digital converter (ADC) to an output digital code, the method comprising:

• at a first ADC internal to the multi-stage ADC, receiving the analog input value and converting the analog input value to a first digital code;
• at a first digital-to-analog converter (DAC) internal to the multi-stage ADC, converting the first digital code to a first analog value;
• at a first linearization module, receiving the first digital code and producing a first linear-correction code that is approximately equal to the first analog value, wherein the first linearization module stores linear-correction codes previously determined by measuring output values produced by the first DAC in response to receiving multiple digital input values, the linear-correction codes including the first linear-correction code;
• at a second ADC internal to the multi-stage ADC, receiving a remainder portion of the analog input value and converting the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;
• at a second linearization module, receiving the second digital code and producing a second linear-correction code;
• and
• combining the first linear-correction code and the second linear-correction code to produce the output digital code.