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US 7,352,299 B1Granted
Method and system for improving memory interface data integrity
AssigneeAltera Corporation
InventorHui Liu
Life of this patent
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AssigneeAltera Corporation
InventorHui Liu
Estimating the term…
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder sets a status bit to indicate that the data are encoded. The encoder includes two encoding stages to further enhance the data integrity and transfer. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, including the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data. The decoder is connected in series with the parity checker.
An integrated circuit (IC) providing optimized data presentation to an external memory interface bus, comprising:
A method for optimizing a data sequence for presentation to an external memory, comprising method operations of:
A method for minimizing simultaneously switching output (SSO) effect on a bus, comprising method operations of:
Dependencies are inferred from the claim text.