Systems and methods for suppressing feedback and reference noise in a phase lock loop circuit
AssigneeTexas Instruments Incorporated
InventorsKoushik Krishnan, Prasun Kali Battacharya
Life of this patent
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Abstract
Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an oscillation control source, and a sample and hold circuit. The sample and hold circuit is disposed between the oscillation control source and the controllable oscillator, and is operable to introduce a transfer function having a sin x/x characteristic with a null at a switch frequency applied to the sample and hold circuit.
Claims16
A system for clock management, the system comprising:
- a controllable oscillator;
- an oscillation control source;
- and
- a sample and hold circuit disposed between the oscillation control source and the controllable oscillator, wherein the system forms at least a portion of a sigma-delta phase lock loop circuit.
A system for clock management, the system comprising:
- a controllable oscillator;
- an oscillation control source;
- and
- a sample and hold circuit disposed between the oscillation control source and the controllable oscillator, wherein the sample and hold circuit is operable to introduce a transfer function having a sin x/x characteristic with a null at the switch frequency.
A method for clock management, the method comprising:
- providing a phase lock loop circuit, wherein the phase lock loop circuit includes:
- a controllable oscillator;
- an oscillation control source;
- and
- a sample and hold circuit disposed between the controllable oscillator and the oscillation control source, wherein the sample and hold circuit introduces a transfer function in the phase lock loop circuit with a sin x/x characteristic with a null at the switch frequency;
- and
- applying a switch frequency to the sample and hold circuit, wherein a signal received from the oscillation control source is sampled and held for application to the controllable oscillator.
A method for clock management, the method comprising,
- providing a phase lock loop circuit, wherein the phase lock loop circuit includes:
- a controllable oscillator;
- an oscillation control source;
- and
- a sample and hold circuit disposed between the controllable oscillator and the oscillation control source, wherein the sample and hold circuit comprising;
- a first switch electrically coupled to the oscillation control source and to a first capacitor;
- and
- a second switch electrically coupled to the first switch, the first capacitor. and the controllable oscillator;
- and
- applying a switch frequency to the sample and hold circuit, wherein a signal received from the oscillation control source is sampled and held for application to the controllable oscillator, wherein applying the switch frequency to the sample and hold circuit includes
- applying a first derivative of the switch frequency to the first switch;
- and
- applying a second derivative of the switch frequency to the second switch.
A phase lock loop circuit, the circuit comprising:
- a phase/frequency detector;
- an oscillation control source, wherein the oscillation control source is electrically coupled to the phase/frequency detector;
- a sample and hold circuit operable to introduce a transfer function having a sin x/x characteristic with a null at the switch frequency, wherein the sample and hold circuit is electrically coupled to the oscillation control source;
- a controllable oscillator, wherein the controllable oscillator is electrically coupled to the sample and hold circuit;
- and
- a divider circuit, wherein the divider circuit is electrically coupled to the phase/frequency detector and to the controllable oscillator.
Dependencies are inferred from the claim text.