Method and apparatus for maintaining a clock/data recovery circuit frequency during transmitter low power mode

A clock control circuit having a differential signal input including a true signal input and a complement signal input, comprising:

• a) a difference detector configured to determine a magnitude difference in an electrical parameter of said true signal input and said complement signal input, and to compare the determined magnitude difference with a predetermined maximum difference;
• b) a frequency detector coupled to receive an output of said difference detector, configured to receive a reference clock and to provide a frequency detection signal indicative of a frequency difference between said reference clock and an frequency output from a variable frequency oscillator;
• and
• c) a selector circuit configured to receive said frequency detection signal and a phase adjustment signal indicative of a phase difference between said differential signal input and said frequency output from said variable frequency oscillator, and to provide a clock control signal for said variable frequency oscillator therefrom.

A clock control circuit, comprising:

• a) a phase detector configured to receive a differential input including a true signal input and a complement signal input, and to output a phase adjustment signal, and having a first enable input;
• b) a frequency detector configured to receive a reference clock and provide a frequency detection signal, said frequency detector having a second enable input;
• c) a difference detector coupled to receive said differential input, and to issue a first control signal if it determines that a magnitude difference in an electrical parameter of said true signal input and said complement signal input is maintained lower than a predetermined value for longer than a predetermined time duration, and to issue a second control signal otherwise, wherein said said frequency detector is enabled in response to said first control signal and is disabled in response to said second control signal;
• d) a combining circuit configured to receive said phase adjustment signal and said frequency detection signal and to provide a clock control signal therefrom.