Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique

A power amplifier, comprising:

• an amplifying block with N transistors connected in parallel to receive and amplify an input signal individually;
• a switching block that forms a cascode configuration by being connected to the amplifying block in series and that N transistors serially connected to each transistor in the amplifying block are connected in parallel;
• a dynamic bias transistor that is operated by a dynamic gate bias by being connected in series between the switching block and an output end, and that reamplifies and outputs a signal coming from the switching block to the output end;
• and
• a voltage dividing block that includes first and second capacitors connected in series between the output end and an ground, and that allots output signals through the first and second capacitors and provides the dynamic gate bias to a gate of the dynamic bias transistor.