US 7,352,243 B2 · Voltage comparator circuit

Abstract

A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In−, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.

Claims21

Dependent claims

A differential amplifier comprising:

an input differential stage having first and second differential pairs of first and second-conductive types, which are driven by first and second current sources, respectively, and to which a differential input signal is inputted;
a folded cascode-type differential stage electrically connected as a load of differential outputs of said first and second differential pairs, the folded cascade-type differential stage generating folded differential outputs;
and
first and second current mirror circuits of first and second-conductive types connected to first and second power sources, respectively, the folded differential outputs being connected to respective inputs of the first and second current mirror circuits, outputs of the first and second current mirror circuits being connected in common to an output terminal;
wherein neither of the differential outputs and neither of the folded differential outputs is connected between the first mirror circuit and the first power source, and neither of the differential outputs and neither of the folded differential outputs is connected between the second mirror circuit and the second power source.

2 more elements

A voltage comparator comprising a differential amplifier and inverters cascode-connected in multiple stages to an output of said differential amplifier wherein said differential amplifier comprises:

a first differential pair of a first P-channel MOS transistor and a second P-channel MOS transistor;
a second differential pair of a first N-channel MOS transistor and a second N-channel MOS transistor;
a third and fourth N-channel MOS transistors with their respective gates connected in common and connected to a first voltage source;
a third and fourth P-channel MOS transistors with their respective gates connected in common and their respective sources connected in common;
a fifth and sixth P-channel MOS transistors with their respective gates connected in common and connected to a second voltage source;
a first current mirror circuit with its input connected to the drain of said fourth N-channel MOS transistor and its common terminal connected to a first power source;
a second current mirror circuit with its input connected to the drain of said sixth P-channel MOS transistor and its common terminal connected to a second power source;
a first constant current source connected between the sources of said first differential pair connected in common and a first power source;
a second constant current source connected between the sources of said second differential pair connected in common and the second power source;
a third constant current source connected between the source of said third N-channel MOS transistor and the second power source;
and
a fourth constant current source connected between the source of said fourth N-channel MOS transistor and the second power source;
wherein
the drain of the first P-channel MOS transistor, which constitutes said first differential pair, is connected in common to the source of said third N-channel MOS transistor;
the drain of the second P-channel MOS transistor, which constitutes said first differential pair, is connected in common to the source of said fourth N-channel MOS transistor;
the drain of said first N-channel MOS transistor, which constitutes said second differential pair, the drain of said third P-channel MOS transistor, and the source of said fifth P-channel MOS transistor are connected in common;
the drain of said second N-channel MOS transistor, which constitutes said second differential pair, the drain of said fourth P-channel MOS transistor, and the source of said sixth P-channel MOS transistor are connected in common;
the gate of said third P-channel MOS transistor, the drain of said fifth P-channel MOS transistor, and the drain of said third N-channel MOS transistor are connected in common;
an output of said first current mirror circuit and an output of said second current mirror circuit are connected in common to form an output terminal;
the gate of said first P-channel MOS transistor and the gate of said first N-channel MOS transistor are connected in common to form an inverting input terminal;
and
the gate of said second P-channel MOS transistor and the gate of said second N-channel MOS transistor are connected in common to form a noninverting input terminal.

19 more elements

A voltage comparator comprising a differential amplifier and inverters cascode-connected in multiple stages to an output of said differential amplifier wherein said differential amplifier comprises:

a first differential pair of a first P-channel MOS transistor and a second P-channel MOS transistor;
a second differential pair of a first N-channel MOS transistor and a second N-channel MOS transistor;
a third and fourth N-channel MOS transistors with their respective gates connected in common and their respective sources connected in common;
a fifth and sixth N-channel MOS transistors with their respective gates connected in common and connected to a first voltage source;
a third and fourth P-channel MOS transistors with their respective gates connected in common and connected to a second voltage source;
a first current mirror circuit with its input connected to the drain of said sixth N-channel MOS transistor and its common terminal connected to a first power source;
a second current mirror circuit with its input connected to the drain of said fourth P-channel MOS transistor and its common terminal connected to a second power source;
a first constant current source connected between the sources of said first differential pair connected in common and a first power source;
a second constant current source connected between the sources of said second differential pair connected in common and the second power source;
a third constant current source connected between the source of said third P-channel MOS transistor and the first power source;
and
a fourth constant current source connected between the source of said fourth P-channel MOS transistor and the second power source;
wherein
the drain of the first P-channel MOS transistor, which constitutes said first differential pair, is connected in common to the source of said fifth N-channel MOS transistor and the drain of said third N-channel MOS transistor;
the drain of the second P-channel MOS transistor, which constitutes said first differential pair, is connected in common to the source of said sixth N-channel MOS transistor and the drain of said fourth N-channel MOS transistor;
the drain of said first N-channel MOS transistor, which constitutes said second differential pair, and the source of said third P-channel MOS transistor are connected in common;
the drain of the second N-channel MOS transistor, which constitutes said second differential pair, and the source of said fourth P-channel MOS transistor are connected in common;
the gate of said third N-channel MOS transistor is connected in common to the drain of said fifth N-channel MOS transistor and the drain of said third P-channel MOS transistor;
an output of said first current mirror circuit and an output of said second current mirror circuit are connected in common to form an output terminal;
the gate of said first P-channel MOS transistor and the gate of said first N-channel MOS transistor are connected in common to form an inverting input terminal;
and
the gate of said second P-channel MOS transistor and the gate of said second N-channel MOS transistor are connected in common to form a noninverting input terminal.

19 more elements

A voltage comparator comprising a differential amplifier and inverters cascode-connected in multiple stages to the output of said differential amplifier wherein said differential amplifier comprises:

a first differential pair of a first P-channel MOS transistor and a second P-channel MOS transistor;
a second differential pair of a first N-channel MOS transistor and a second N-channel MOS transistor;
a third and fourth N-channel MOS transistors with their respective gates connected in common and connected to a first voltage source;
a first constant current source connected between the sources of said first differential pair connected in common and a first power source;
a second constant current source connected between the sources of said second differential pair connected in common and a second power source;
a third constant current source connected between the source of said third N-channel MOS transistor and the second power source;
a fourth constant current source connected between the source of said fourth N-channel MOS transistor and the second power source;
a first current mirror circuit with its input terminal connected in common to the drain of said first N-channel MOS transistor and the drain of said third N-channel MOS transistor, and its common terminal connected in common to the first power source terminal;
a second current mirror circuit with its input terminal connected in common to the drain of said second N-channel MOS transistor and the drain of said fourth N-channel MOS transistor, and its common terminal connected in common to the first power source terminal;
and
a third current mirror circuit with its input terminal connected to the output terminal of said first current mirror circuit, and its common terminal connected to the second power source;
and
the drain of said first P-channel MOS transistor is connected to the source of said third N-channel MOS transistor;
the drain of said second P-channel MOS transistor is connected to the source of said fourth N-channel MOS transistor;
an output terminal of said second current mirror circuit and an output terminal of said third current mirror circuit are connected in common to form an output terminal;
the gate of said first P-channel MOS transistor and the gate of said first N-channel MOS transistor are connected in common to an inverting input terminal;
and
the gate of said second P-channel MOS transistor and the gate of said second N-channel MOS transistor are connected in common to a noninverting input terminal.

15 more elements

Dependencies are inferred from the claim text.

Voltage comparator circuit

Life of this patent

Voltage comparator circuit

Life of this patent

Abstract

Claims21