US 7,352,227 B2Granted

Semiconductor device having plurality of circuits belonging to different voltage domains

AssigneeKabushiki Kaisha Toshiba

InventorsShinichiro Shiratake, Hiroyuki Hara

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Abstract

A first inverter circuit comprises a first transistor in which one end of a current path is grounded, and a second transistor in which one end of a current path is connected to the other end of the current path of the first transistor. A first signal is supplied to gates of the first and second transistors. A third transistor is connected between the other end of the current path of the second transistor and a node to which a second voltage higher than the first voltage is supplied. A control signal constituted of one of the ground potential and the second voltage is supplied to a gate of the third transistor behind a change of a first signal. A second signal constituted of one of the ground potential and the second voltage is output from an output terminal of the first inverter circuit.

Claims13

Dependent claims

A level conversion circuit comprising:

a first inverter circuit having first and second transistors of first and second conductive types, one end of a current path of the first transistor being grounded, the other end thereof being connected to one end of a current path of the second transistor of the second conducive type, and a first input signal constituted of one of a ground potential and a first voltage higher than the ground potential being supplied to gates of the first and second transistors;
a third transistor of a second conductive type connected between the other end of the current path of the second transistor and a second voltage higher than the first voltage, a control signal constituted of one of the ground potential and the second voltage being supplied to a gate of the third transistor behind a change of the first input signal,
wherein a first output signal constituted of one of the ground potential and the second voltage is output from an output end of the first inverter circuit;
and
a control circuit whose input end is connected to the gates of the first and second transistors and whose output end is connected to the gate of the third transistor,
wherein the control circuit outputs the control signal in accordance with the first input signal,
the control circuit comprising:
a fourth inverter circuit driven by the first voltage, the first input signal being supplied to an input end of the fourth inverter circuit;
a fifth inverter circuit driven by the first voltage, an output signal of the fourth inverter circuit being supplied to an input end of the fifth inverter circuit;
a differential amplifier circuit driven by the second voltage to amplify and output a difference voltage between input and output signals of the fifth inverter circuit;
and
a sixth inverter circuit driven by the second voltage, an output signal of the differential amplifier circuit being supplied to an input end of the sixth inverter circuit, and the control signal being output from an output end thereof.

9 more elements

A semiconductor device comprising:

a first logical circuit driven by a first voltage and a first clock signal to output a second clock signal of the first voltage;
a second logical circuit driven by a second voltage higher than the first voltage and a third clock signal as a reference to output a fourth clock signal of the second voltage;
a level conversion circuit which converts the second clock signal output from the first logical circuit into a second clock signal of the second voltage;
and
a delay control circuit to which the second clock signal of the second voltage output from the level conversion circuit, the fourth clock signal of the second voltage output from the second logical circuit, and the third clock signal are supplied, and which detects a skew amount between the second and fourth clock signals, and which generates the first clock by delaying the third clock in accordance with the detected skew amount between the second and fourth clock signals.

2 more elements

Dependencies are inferred from the claim text.