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US 7,352,219 B2Granted
Duty cycle corrector
AssigneeInfineon Technologies AG
InventorAlessandro Minzoni
Life of this patent
Estimating the term…
Abstract
A duty cycle corrector including a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type. A delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock. An adjuster circuit configured to receive the differential input and feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle.
Claims18
A duty cycle corrector comprising:
- a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type;
- a delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock;
- and
- an adjuster circuit configured to receive the differential input and differential feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle;
- and
- wherein the restore circuit comprises:
- a first operational amplifier receiving the differential input clock and providing a first output having a first state in response to differential input clock crossings of the first type and having a second state in response to differential input clock crossings of the second type;
- a second operational amplifier receiving the differential feedback clock and providing a second output having the first state in response to differential feedback crossings of the second type and having the second state in response to differential feedback crossings of the first type;
- and
- a signal generator providing the differential output clock based on the states of the first and second outputs.
7 more elements
A duty cycle corrector comprising:
- a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type;
- a delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock;
- and
- an adjuster circuit configured to receive the differential input and differential feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle;
- wherein the adjuster circuit comprises:
- a phase detector configured to determine a phase difference between differential input crossings of the first type and differential feedback crossings of the second type and to provide a control signal having a value based on based on the phase difference;
- and
- a counter configured to adjust the delay time of the delay element based on the control signal value;
- and
- wherein the phase detector comprises:
- a first operational amplifier receiving the differential input clock and providing a first output having a first state in response to differential input clock crossings of the first type and having a second state in response to differential input clock crossings of the second type;
- a second operational amplifier receiving the differential feedback clock and providing a second output having the first state in response to differential feedback crossings of the second type and having the second state in response to differential feedback crossings of the first type;
- and
- a signal generator providing the control signal having a value based a time difference the first output transitioning from the second state to the first state and the second output transitioning from the second state to the first state.
11 more elements
A duty cycle corrector comprising:
- a first restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossings of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type;
- a delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock;
- a second restore circuit configured to receive the differential input clock and to provide a restored input clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential input clock crossings of the second type;
- an adjuster circuit configured to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle.
1 more element
A memory circuit comprising:
- a memory;
- a first restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and crossings of a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type;
- a second restore circuit configured to receive the differential input clock and to provide a restored input clock having crossings of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential input clock crossings of the second type;
- a delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock;
- and
- an adjuster circuit configured to receive the restored input and differential feedback clocks and to adjust the delay time based on a phase difference between restored input clock crossings of the first type and differential feedback clock crossing of the second type so as to maintain a duty cycle of the differential output clock substantially at a fifty percent duty cycle, wherein the adjuster circuit adjusts the delay time so as to substantially align differential feedback crossings of the second type with differential input clock crossings of the first type.
3 more elements
Dependencies are inferred from the claim text.