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US 7,352,218 B2Granted
DLL circuit and method of controlling the same
AssigneeHynix Semiconductor Inc.
InventorHoon Choi
Life of this patent
Estimating the term…
Abstract
A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.
Claims17
A DLL (Delay Locked Loop) circuit comprising:
- a buffer control unit configured to detect whether or not a voltage level of the DLL power supply exceeds a reference level and enable a buffer control signal;
- and
- a clock buffer configured to buffer an external clock to generate an internal clock when the buffer control signal is enabled.
A DLL (Delay Locked Loop) circuit comprising;
- a buffer control unit configured to control whether or not to output a buffer enable signal generated on the basis of a clock enable command according to whether or not a voltage level of a DLL power supply exceeds a reference level;
- and
- a clock buffer configured to buffer an external clock to generate an internal clock when the buffer enable signal is input to the clock buffer.
A method of controlling a DLL (Delay Locked Loop) circuit, comprising:
- dividing an external power supply voltage to generate a divided voltage;
- comparing the voltage level of a DLL power supply with a voltage level of the divided voltage and controlling output of a buffer enable signal based on the comparison;
- and
- buffering an external clock to generate an internal clock when the buffer enable signal is input.
1 more element
Dependencies are inferred from the claim text.