Lock phase circuit

A phase lock circuit, comprising:

• input means for receiving an input phase lock signal;
• timing means for generating a timing signal;
• means for generating a phase lock pulse based on the phase lock signal and the timing signal;
• and
• a phase indeterminate means in communication with the timing means and the means for generating a phase lock pulse, the phase indeterminate means for generating an output signal based on the phase lock pulse and having a known phase relationship to the timing signal.

A method of testing a circuit, comprising:

• receiving a phase lock signal on a circuit input;
• receiving a clock signal;
• generating a phase lock pulse based on the phase lock signal and the clock signal;
• receiving the phase lock pulse in a phase indeterminate circuit element;
• and
• generating an output of the phase indeterminate circuit element, the output of the phase indeterminate circuit element having a known phase relationship to the clock signal.

A phase lock circuit, comprising:

• an input configured to receive a phase lock signal;
• a clock configured to generate a clock signal;
• phase lock circuitry in communication with the input and the clock, the phase lock circuitry configured to generate a phase lock pulse based on the phase lock signal and the clock signal, wherein the phase lock circuitry comprises:
• sampling circuitry configured to generate a sampling output based on the phase lock signal, the sampling output having a known phase relationship to the clock signal, and
• pulse generation circuitry configured to generate the phase lock pulse based on the sampling output;
• and
• a phase indeterminate circuit element, the phase indeterminate circuit element configured to receive the phase lock pulse and to generate an output signal based on the phase lock pulse, the output signal having a known phase relationship to the clock signal.

A phase lock circuit, comprising:

• an input configured to receive a phase lock signal;
• a clock configured to generate a clock signal;
• phase lock circuitry in communication with the input and the clock, the phase lock circuitry configured to generate a phase lock pulse based on the phase lock signal and the clock signal, wherein the phase lock circuitry comprises:
• pulse generation circuitry configured to generate an output pulse based on the phase lock signal, and
• sampling circuitry configured to generate the phase lock pulse based on the output pulse, the phase lock pulse having a known phase relationship to the clock signal;
• and
• a phase indeterminate circuit element, the phase indeterminate circuit element configured to receive the phase lock pulse and to generate an output signal based on the phase lock pulse, the output signal having a known phase relationship to the clock signal.

A phase lock circuit, comprising:

• input means for receiving an input phase lock signal;
• timing means for generating a timing signal;
• means for generating a phase lock pulse based on the phase lock signal and the timing signal, wherein the means for generating the phase lock pulse based on the phase lock signal and the timing signal comprises:
• sampling means for generating a sampling output based on the phase lock signal, the sampling output having a known phase relationship to the timing signal, and
• pulse generation means for generating the phase lock pulse based on the sampling output;
• and
• a phase indeterminate means in communication with the timing means and the means for generating a phase lock pulse, the phase indeterminate means for generating an output signal based on the phase lock pulse and having a known phase relationship to the timing signal.

A phase lock circuit, comprising:

• input means for receiving an input phase lock signal;
• timing means for generating a timing signal;
• means for generating a phase lock pulse based on the phase lock signal and the timing signal, wherein the means for generating the phase lock pulse based on the phase lock signal and the timing signal comprises:
• means for generating an output pulse based on the phase lock signal, and
• sampling means for generating the phase lock pulse based on the output pulse, the phase lock pulse having a known phase relationship to the timing signal;
• and
• a phase indeterminate means in communication with the timing means and the means for generating a phase lock pulse, the phase indeterminate means for generating an output signal based on the phase lock pulse and having a known phase relationship to the timing signal.

A method of testing a circuit, comprising:

• receiving a phase lock signal on a circuit input;
• receiving a clock signal;
• generating a phase lock pulse based on the phase lock signal and the clock signal, wherein generating the phase lock pulse based on the phase lock signal and the clock signal comprises:
• generating a first signal based on the phase lock signal and the clock signal, and
• generating the phase lock pulse based on the first signal;
• receiving the phase lock pulse in a phase indeterminate circuit element;
• and
• generating an output of the phase indeterminate circuit element, the output of the phase indeterminate circuit element having a known phase relationship to the clock signal.

A method of testing a circuit, comprising:

• receiving a phase lock signal on a circuit input;
• receiving a clock signal;
• generating a phase lock pulse based on the phase lock signal and the clock signal, wherein generating the phase lock pulse based on the phase lock signal and the clock signal comprises:
• generating a first pulse based on the phase lock signal, and
• generating the phase lock pulse based on the first pulse;
• receiving the phase lock pulse in a phase indeterminate circuit element;
• and
• generating an output of the phase indeterminate circuit element, the output of the phase indeterminate circuit element having a known phase relationship to the clock signal.