High speed ramp generator
AssigneeTeridian Semiconductor Corporation
InventorRussell Hershbarger
Life of this patent
Estimating the term…
Abstract
A high speed ramp generator is presented. The high speed ramp generator is advantageous over the prior art because it provides a ramp response without the delay incident with a simple integrator approach. A closed loop system generates a continuous ramp and, in an open loop manner, subtracts a mirror of the current ramp from itself. A switch is provided which when open, triggers an immediate current ramp output that is not dependent on the amplifier or any other component of prior art feedback circuits. Two such ramp generators may be used in tandem to provide alternating portions of a precision ramp signal, such as may be used to cancel the magnetization current induced in the primary of an isolation transformer.
Claims20
A current ramp apparatus comprising:
- an integrator receiving an input signal and providing a first ramp current to an output node, said first ramp current having a ramp rate proportional to said input signal;
- and
- a current mirror circuit configured to provide a second current to said output node, said second current having an equivalent magnitude and opposite polarity of said first ramp current, said current mirror circuit configured to hold said second current at a constant value when a control signal is asserted.
A ramp generation method comprising:
- integrating an input signal in an integrator to provide a first ramp current to a first output node, said first ramp current having a ramp rate proportional to said input signal;
- providing an opposing current signal to said first output node from a current mirror circuit, said opposing current signal having an opposite polarity with respect to said first ramp current;
- said opposing current signal tracking a magnitude of said first ramp current to provide a zero output current value from said first output node during a setup phase;
- and
- providing a net ramp output current from said first output node by freezing said opposing current signal at a constant current value during a ramp phase.
A ramp signal apparatus comprising:
- a first ramp generator configured to provide a first ramp current that ramps from zero to a peak ramp value during a first phase, said first ramp generator providing zero current during a second phase;
- a second ramp generator configured to provide a second ramp current that ramps from zero to said peak ramp value during said second phase, said second ramp generator providing zero current during said first phase;
- a current driver coupled to said first ramp generator and said second ramp generator, said current driver comprising:
- a peak current track-and-hold circuit configured to track said peak ramp value from said first ramp current during said first phase and provide a constant peak current equivalent to said peak ramp value during said second phase;
- a summing circuit configured to subtract said second ramp current from said constant peak current to provide a third ramp current that ramps from said peak ramp value to zero during said second phase.
Dependencies are inferred from the claim text.