Reconfigurable switching device parallel calculation of any particular algorithms

A reconfigurable architecture for a computer device having at least one individually configurable and/or reconfigurable sequential circuit which

• has a first stage with inputs and is formed from a plurality of parallel-connected memory elements which can be addressed via input lines, each memory element being able to be supplied with a subset of input variables attached to an associated, ascertained implicant,
• has a second stage, connected downstream of the first stage, with memory elements which can be addressed by identifiers of the individual implicants, and
• has a third stage, connected downstream of the second stage, with outputs and with means for disjunctive logic combination of output values from the individual implicants from the memory elements in the second stage,
• where output variables from at least some of the outputs at a time tn-1 form the input variables on associated inputs of the sequential circuit at a time tn and where means are provided for clock-controlled storage of the output variables from the sequential circuit between the times tn-1 and tn.