System and method for testing devices utilizing capacitively coupled signaling

#The present invention is related to testing semiconductor devices, and more particularly, to a system and method for testing semiconductor devices utilizing capacitively coupled signaling, such as in a system-in-package device.

#Traditional semiconductor integrated circuit technology is used to integrate various electronic circuits onto a common semiconductor substrate to form a system, or subsystem. However, the traditional approach to integrating circuits into a system has process, manufacturing and design limitations which make integrating some electronic circuitry onto a common semiconductor substrate impractical. A new integration technology, namely, system-in-package (SiP) technology, attempts to overcome the limitations of the traditional approach by interconnecting multiple discrete semiconductor systems on a common substrate and encapsulating the complete system in a common package. Generally, SiP enables the integration of a mix of technologies into one package that would otherwise be difficult and expensive using the traditional approach. For example, SiP technology has been successfully applied in mixed signal applications, such as RF/wireless applications and sensor applications, as well as in networking and computing applications, and other high speed digital applications.

#As previously mentioned, the multiple discrete systems of a SiP are electrically coupled together to form a system and, as is well known in the art of digital electronics, many of the multiple systems communicate with one another by transmitting digital information in the form of electrical signals. Typically, even analog based systems included in the SiP have the analog signals converted into the digital domain. The electrical signals transmitted between the multiple systems represent a serial data stream where the data is represented as binary symbols having discrete levels of amplitude or phase, as well known. Multiple electrical signals are transmitted in parallel to transmit data of a data width, with each signal representing one bit of the width of data. In transmitting the data, the electrical signal is often distorted by various phenomena, such as noise, signal strength variations, phase shift variations, and the like. Additionally, in a SiP device, where multiple individual devices interact, the various devices may operate in different voltage domains and potentially cause electrical currents to flow from one system to another. Not only do the currents result in unwanted current (i.e., power) consumption, in some cases the current may be great enough to cause damage to one of the devices.

#FIG. 1 is a schematic drawing of a conventional capacitively coupled data bus.

#FIG. 2 is a partial isometric and cross-sectional view of a semiconductor structure of a system-in-package device including an embodiment of the present invention.

#FIG. 3 is a partial isometric and cross-sectional view of a semiconductor structure according to an embodiment of the present invention for use in a capacitively coupled signaling system.

#FIG. 2 is a partial isometric and cross-sectional view illustrating a portion of a SiP 500. It will be appreciated that the lateral sizes and thickness of the various layers illustrated in the accompanying figures are not drawn to scale and these various layers or layer portions may have been enlarged or reduced to improve drawing legibility. It will be further appreciated that in the following description, many of the processing steps discussed are understood by those of ordinary skill in the art, and detailed descriptions thereof have been omitted for the purposes of unnecessarily obscuring the present invention.

#The SiP 500 includes a first semiconductor device, represented by semiconductor structure 200, capacitively coupled to a second semiconductor device, represented by a semiconductor structure 520. The semiconductor structures 200, 520 are capacitively coupled through a dielectric 522. As shown in FIG. 2, the semiconductor structure 200 is included in a first semiconductor device and the semiconductor structure 520 is included in a second semiconductor device. A more detailed description of the die-to-die bonding process used in forming the structure of the SiP 500 can be found in commonly assigned, UK Patent Application No. 0323992.8, entitled STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE to Neaves, which is incorporated herein by reference. In summary, signal pads 202, 206 are formed on the semiconductor structure 200, and signal pads 502, 506 are formed on the semiconductor structure 520, such that when bonding of the two devices occurs, the signal pads 202 and 502 are positioned to be capacitively coupled together, and the signal pads 206 and 506 are positioned to be capacitively coupled together. Thus, employing the die-to-die bonding technique described in the aforementioned co-pending U.S. patent application eliminates the need to use discrete capacitors in forming a capacitively coupled signaling system between the semiconductor structure 200 to the semiconductor structure 520.

#As shown in FIG. 2, the semiconductor structure 200 represents an embodiment of the present invention which can be used with a capacitively coupled signaling system. FIG. 2 illustrates the semiconductor structure 200 implemented in a SiP 500 formed in accordance with the previously described co-pending U.S. Patent Application. The device on which the semiconductor structure 200 is included represents a transmitting device, and the device on which the semiconductor structure 520 is included represents a receiving device. Each of the signal pads 502, 506 are coupled to a respective receiver 114 that provides a data signal D_IN0, D_IN1, respectively. A grounded conductive plate layer 510 is formed in proximity to the signal pads 502, 506 to provide a well defined ground plane. In the semiconductor structure 200, the signal pads 202, 206 are coupled to a respective transmitter 112, each of which receives a data signal, D_OUT0, D_OUT1. A conductive plate layer 210 is formed in proximity of the signal pads 202, 206, and is separated therefrom by a dielectric material.