Testing components of I/O paths of an integrated circuit
AssigneeTexas Instruments Incorporated
InventorsJais Abraham, Rohit Goel
Life of this patent
Estimating the term…
Abstract
Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.
Claims10
A method of testing an integrated circuit containing a plurality of input/output (I/O) paths, each of said I/O paths being provided between corresponding a I/O pad and an internal functional logic also contained in said integrated circuit, each of said I/O paths containing a corresponding conductor, a corresponding scan cell and a corresponding component, said method comprising:
- placing said scan cells in the form of a chain, wherein said scan cells contain a first scan cell having a first component as said corresponding component;
- scanning-in a scan vector to set each of said scan cells to a corresponding bit value, wherein said first scan cell is set to a first value;
- launching said first value on to said first component from said first scan cell at a first time instance;
- capturing in a register an output of said first component at a second time instance, wherein said second time instance is timed to correspond to an at-speed operation of said integrated circuit;
- comparing said output with an expected value to determine whether said first component is operating accurately at said at-speed operation.
A computer readable medium carrying one or more sequences of instructions for enabling a tester to test an integrated circuit containing a plurality of input/output (I/O) paths, each of said I/O paths being provided between corresponding a I/O pad and an internal functional logic also contained in said integrated circuit, each of said I/O paths containing a corresponding conductor, a corresponding scan cell and a corresponding component, wherein execution of said one or more sequences of instructions by one or more processors contained in a system causes said one or more processors to perform the actions of:
- placing said scan cells in the form of a chain, wherein said scan cells contain a first scan cell having a first component as said corresponding component;
- scanning-in a scan vector to set each of said scan cells to a corresponding bit value, wherein said first scan cell is set to a first value;
- launching said first value on to said first component from said first scan cell at a first time instance;
- capturing in a register an output of said first component at a second time instance, wherein said second time instance is timed to correspond to an at-speed operation of said integrated circuit;
- comparing said output with an expected value to determine whether said first component is operating accurately at said at-speed operation.
An integrated circuit containing:
- a plurality of input/output (I/O) pads;
- a functional internal logic;
- a plurality of components, each component being located in an I/O path provided between a corresponding one of said I/O pads and said functional internal logic;
- and
- a plurality of scan cells designed to be connected as a scan chain, each of said plurality of scan cells being connected to send a data bit to a corresponding one of said plurality of components at a first time instance and latch an output received from said component at a second time instance,
- wherein said first time instance and said second time instance are timed to correspond to an at-speed operation of said integrated circuit such that each of said plurality of scan cells is used to test said corresponding one of said plurality of components at said at-speed operation.
Dependencies are inferred from the claim text.