US 7,352,058 B2Granted

Methods for a multiple die integrated circuit package

AssigneeSanDisk Corporation

InventorBob Wallace

Life of this patent

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Abstract

Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.

Claims13

Dependent claims

A method for forming a multiple die integrated circuit package comprising the steps of:

providing an insulator layer having a first surface and a second opposing surface;
forming one or more through-hole vias in said insulator layer at desired locations;
providing a first leadframe having a plurality of leads at least partially overlying said first surface;
providing a second leadframe having a plurality of leads at least partially overlying said second surface;
coupling a first integrated circuit die to at least one lead of said first leadframe;
coupling a second integrated circuit die to at least one lead of said second leadframe;
deforming a lead of the first leadframe, at a position covering a through-hole via, into the through-hole via;
electrically connecting the lead deformed into the via to a corresponding lead of the second leadframe through the through-hole via in said insulator;
whereby the first and second integrated circuit dies are electrically coupled to one another.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/264,556Filed 1 Nov 2005
Published: US 2007/0096284 A13 May 2007
Granted: 1 Apr 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 70/442
Shapes or dispositions: of multiple leadframes in a single chip
H10W 70/413
Chip-supporting parts, e.g. die pads: insulating or insulated substrates serving as die pads
H10W 70/415
Chip-supporting parts, e.g. die pads: leadframe inner leads serving as die pads
H10W 90/811
Package configurations: multiple chips on leadframes