Twin MONOS array for high speed application

A twin MONOS metal bit array structure comprising:

• a plurality of memory cells two dimensionally disposed in a first direction, wherein memory cells adjacent in said first direction are separated by isolation regions, and in a second direction crossing said first direction perpendicularly;
• a plurality of metal bit line pairs;
• a plurality of substrate silicon isolations in substrate silicon configured in straight lines and isolated said substrate silicon stripes in between configured in straight lines wherein a pitch of said isolation is equal to two pitches of said metal bit line pairs;
• a plurality of conductive word gate lines crossing over said isolations and gate oxide overlying said silicon stripes extending in said second direction;
• a plurality of pairs of conductive control gate lines on sidewalls of said word gate lines extending in said second direction;
• a plurality of diffusion regions having opposite polarity to a polarity of said substrate silicon wherein said diffusion regions are located in said isolated silicon stripes between adjacent said conductive control gate lines in said first direction;
• and
• channels between adjacent said diffusion regions underlying said word gate lines and said control gates.