US 7,352,026 B2 · EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same

Abstract

Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Claims15

Dependent claims

An electrically erasable and programmable read only memory (EEPROM) cell comprising:

a substrate including a first region, in which a first EEPROM device having a first select transistor and a first memory transistor is disposed, and a second region, in which a second EEPROM device having a second select transistor and a second memory transistor is disposed;
a first drain region and a first floating region, which are disposed apart from each other in the first region of the substrate;
a second drain region and a second floating region, which are disposed apart from each other in the second region of the substrate;
and
a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region, which are disposed between the first region and the second region of the substrate,
wherein the first impurity region completely surrounds the second impurity region and the third impurity region in horizontal and vertical directions and a junction depth of the first impurity region is greater than a junction depth of the fourth impurity region, the second impurity region surrounds the third impurity region in the horizontal direction, and the junction depth of the third impurity region is greater than the junction depth of the second impurity region;
and
wherein the fourth impurity region is formed using a dopant of a different conductivity type from those of the first, second, and third impurity regions.

5 more elements

An EEPROM device comprising:

a substrate including a memory cell region, in which an EEPROM cell including a first EEPROM device and a second EEPROM device is disposed, and a peripheral circuit region, in which a high-voltage MOS transistor and a low-voltage MOS transistor are disposed;
a common source region, which includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region between the first EEPROM device and the second EEPROM device of the memory cell region, wherein the first impurity region completely surrounds the second impurity region and the third impurity region in horizontal and vertical directions and a junction depth of the first impurity region is greater than a junction depth of the fourth impurity region, the second impurity region surrounds the third impurity region in the horizontal direction, and the junction depth of the third impurity region is greater than the junction depth of the second impurity region;
source/drain regions of the high-voltage MOS transistor, each of which includes a first impurity region and a third impurity region that is completely surrounded by the first impurity region in the horizontal and vertical directions;
and
source/drain regions of the low-voltage MOS transistor, each of which includes a second impurity region and a third impurity region that is surrounded by the second impurity region but has a greater junction depth than the second impurity region;
and
wherein the fourth impurity region is formed using a dopant of a different conductivity type from those of the first, second, and third impurity regions.

4 more elements

Dependencies are inferred from the claim text.

EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same

Life of this patent

EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same

Life of this patent

Abstract

Claims15