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US 7,352,025 B2Granted
Semiconductor memory device with increased node capacitance
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Andres Bryant, Edward J. Nowak
Life of this patent
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Abstract
An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without requiring a corresponding increase in area.
Claims14
An integrated circuit semiconductor memory device provided with a semiconductor fin comprising:
- a substrate;
- a first dielectric layer covering a first portion of said substrate, said first dielectric layer being absent from a second portion of said substrate;
- a second dielectric layer having a property different from said first dielectric layer, said second dielectric layer at least partly covering said second portion of said substrate;
- a source region formed in a first doped region on said first dielectric layer;
- a drain region formed in a second doped region on said first dielectric layer;
- and
- a gate formed over said second dielectric layer and between said first and second doped regions,
- wherein said substrate has an upwardly facing first surface at an upper level and an upwardly facing second surface at a lower level, said first dielectric layer being a dielectric layer formed on said first surface, said second dielectric layer being a dielectric layer formed on said second surface, and said fin being formed over said first dielectric layer.
5 more elements
Dependencies are inferred from the claim text.