US 7,352,018 B2 · Non-volatile memory cells and methods for fabricating non-volatile memory cells

Abstract

The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.

Claims32

Dependent claims

A memory cell arrangement, comprising:

a fin structures, comprising:
a first semi-conductive region in a first direction;
an insulating layer disposed above the first semi-conductive region in the first direction;
and
a second semi-conductive region disposed above the insulating layer in the first direction, the second semi-conductive region being electrically isolated from the first semi-conductive region;
a charge storage layer structure disposed above a portion of the fin structure in a second direction, the second direction being different from the first direction, wherein the fin structure further comprises first source/drain regions within the first semi-conductive region adjacent to the charge storage layer structure and second source/drain regions within the second semi-conductive region adjacent to the charge storage layer structure;
and
a control gate disposed above the charge storage layer structure in the second direction.

5 more elements

A NAND memory cell arrangement, comprising:

a fin structure comprising:
a plurality of first semi-conductive regions coupled in series with one another along a length of the fin structure in a first direction;
an insulating layer disposed above the first semi-conductive regions in the first direction;
and
a plurality of second semi-conductive regions disposed above the insulating layer in the first direction, the second semi-conductive regions being coupled in series with one another, wherein the second semi-conductive regions are electrically isolated from the first semi-conductive regions;
a plurality of charge storage layer structures above the fin structure in a second direction, the second direction being different from the first direction, each charge storage layer structure being disposed above a respective one of the first semi-conductive regions and a respective one of the second semi-conductive regions;
first source/drain regions within the first semi-conductive regions adjacent to the charge storage layer structures;
second source/drain regions within the second semi-conductive regions adjacent to the charge storage layer structures;
and
a plurality of control gates, each control gate being disposed above a respective one of the charge storage layer structures in the second direction.

7 more elements

Dependencies are inferred from the claim text.

Non-volatile memory cells and methods for fabricating non-volatile memory cells

Life of this patent

Non-volatile memory cells and methods for fabricating non-volatile memory cells

Life of this patent

Abstract

Claims32