Semiconductor transistors having reduced channel widths and methods of fabricating same

A method of fabricating a semiconductor device comprising:

• disposing a masking layer over a substrate;
• patterning the masking layer to form an opening therethrough;
• disposing a screening layer over the masking layer and the substrate, wherein the screening layer comprises a thickness;
• implanting a first type of ions into the substrate through the screening layer and through the opening in the masking layer to form an N+ doped source region in the substrate;
• and
• forming a channel by implanting a second type of ions in the substrate through the screening layer and through the opening in the masking layer at an oblique ion implantation angle to form a P-type well region in the substrate.

A semiconductor device comprising:

• at least one semiconductor layer;
• a patterned masking layer over the at least one semiconductor layer, wherein the patterned masking layer has an opening therethrough, wherein the opening has a first width;
• a screening layer over the at least one semiconductor layer and the patterned masking layer, wherein the screening layer is in a range of about 100 Å to about 7000 Å thick;
• a first ion implanted region in the at least one semiconductor layer arranged below the opening, wherein the first ion implanted region comprises a second width that is less than or equal to the first width;
• and
• a second ion implanted region in the at least one semiconductor layer arranged below the opening and around the first ion implanted region, wherein the second ion implanted region comprises a third width that is greater than the first width.