Methods of forming semiconductor constructions
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
Claims13
A method of forming a semiconductor construction, comprising:
- providing a substrate;
- forming an insulative material over the substrate;
- forming a crystalline layer over the insulative material;
- the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium;
- forming a field effect transistor having a transistor gate and a pair of source/drain regions;
- the field effect transistor gate being over the crystalline layer, and the field effect transistor having an active region extending into the crystalline layer;
- at least a portion of the source/drain regions being comprised by the active region within the crystalline layer;
- the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium;
- and
- forming a bipolar transistor having a collector region, emitter region and a base region;
- the collector region and emitter region both being elevationally above the transistor gate;
- the base region electrically connecting with one of the source/drain regions of the field effect transistor.
A method of forming a semiconductor construction, comprising:
- forming an insulative material over a substrate;
- forming a crystalline layer over the insulative material;
- the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium;
- forming a field effect transistor having a transistor gate and a pair of source/drain regions;
- the field effect transistor gate being over the crystalline layer, and the field effect transistor having an active region extending into the crystalline layer;
- at least a portion of the source/drain regions being comprised by the active region within the crystalline layer;
- the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium;
- forming a bipolar transistor having a collector region, emitter region and a base region;
- the collector region and emitter region both being elevationally above the transistor gate;
- the base region electrically connecting with one of the source/drain regions of the field effect transistor;
- and
- wherein the material which includes silicon and germanium comprises from about 10 to about 60 atomic percent germanium.
A method of forming a semiconductor construction, comprising:
- forming an insulative material over a substrate;
- forming a crystalline layer over the insulative material;
- the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium;
- wherein the crystalline layer has a relaxed crystalline lattice;
- forming a strained crystalline lattice layer over the relaxed crystalline lattice;
- forming a field effect transistor having a transistor gate and a pair of source/drain regions;
- the field effect transistor gate being over the crystalline layer, and the field effect transistor having an active region extending into the crystalline layer;
- at least a portion of the source/drain regions being comprised by the active region within the crystalline layer;
- the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium;
- the field effect transistor gate being formed over the strained crystalline lattice layer;
- and
- forming a bipolar transistor having a collector region, emitter region and a base region;
- the collector region and emitter region both being elevationally above the transistor gate;
- the base region electrically connecting with one of the source/drain regions of the field effect transistor.
Dependencies are inferred from the claim text.