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US 7,351,291 B2Granted
Semiconductor processing system
AssigneeTokyo Electron Limited
InventorSeishi Murakami
Life of this patent
Estimating the term…
Abstract
A semiconductor processing system includes a load lock chamber and first to third process chambers connected to an airtight transfer chamber. The second process chamber is disposed below the first process chamber and overlaps with the first process chamber. The third process chamber is disposed at a position laterally distant from the first process chamber and leveled with the first process chamber. First to third exhaust ports are formed in the bottoms of the first to third process chambers, and connected to respective vacuum exhaust sections through first to third exhaust lines. A transfer mechanism is disposed in the transfer chamber to transfer a target substrate to and from the load lock chamber and the first to third process chambers.
Claims13
A semiconductor processing system comprising:
- a pressure-adjustable airtight transfer chamber having a polygonal plan-view contour including first, second, and third planar faces each forming a distinct plane;
- a pressure-adjustable load lock chamber connected to an in/out port, which is formed in the first planar face, through a gate valve, and configured to insert/receive a target substrate into/from the transfer chamber;
- a pressure-adjustable first process chamber connected to a first port, which is formed in the second planar face, through a gate valve, and configured to subject a target substrate to a semiconductor process in a vacuum atmosphere;
- a pressure-adjustable second process chamber connected to a second port, which is formed in the second planar face and shifted in a position from the first port in a first horizontal direction along the second planar face, through a gate valve, and configured to subject a target substrate to a semiconductor process in a vacuum atmosphere, the second process chamber being disposed below the first process chamber and overlapping with the first process chamber as viewed in a vertical direction along the second planar face, and the second process chamber having a center shifted from that of the first process chamber in the first horizontal direction along the second planar face;
- a pressure-adjustable third process chamber connected to a third port, which is formed in the third planar face, through a gate valve, and configured to subject a target substrate to a semiconductor process in a vacuum atmosphere, the third process chamber being disposed at a position laterally distant from the first process chamber, the third port being substantially leveled with the first port or the second port;
- first to third exhaust lines respectively connecting first to third exhaust ports formed in bottoms of the first to third process chambers to corresponding vacuum exhaust sections;
- and
- a transfer mechanism disposed in the transfer chamber, and configured to transfer a target substrate to and from the load lock chamber and the first to third process chambers,
- wherein an offset space is formed below the first process chamber and beside an adjacent sidewall of the second process chamber, and the first exhaust line extends downward through the offset space,
- the first exhaust port is disposed at a substantial center of the first process chamber, and
- a gas convergence portion is formed below the first exhaust port, and the first exhaust line includes a first portion extending horizontally from the gas convergence portion to the offset space, and a second portion extending downward from the first portion through the offset space.
8 more elements
A semiconductor processing system comprising:
- a pressure-adjustable airtight transfer chamber having a polygonal plan-view contour including first and second planar faces each forming a distinct plane;
- a pressure-adjustable load lock chamber connected to an in/out port, which is formed in the first planar face, through a gate valve, and configured to insert/receive a target substrate into/from the transfer chamber;
- a pressure-adjustable first process chamber connected to a first port, which is formed in the second planar face, through a gate valve, and configured to subject a target substrate to a semiconductor process in a vacuum atmosphere;
- a pressure-adjustable second process chamber connected to a second port, which is formed in the second planar face and shifted in position from the first port in a first horizontal direction along the second planar face, through a gate valve, and configured to subject a target substrate to a semiconductor process in a vacuum atmosphere, the second process chamber being disposed below the first process chamber and overlapping with the first process chamber as viewed in a vertical direction along the second planar face, and the second process chamber having a center shifted from that of the first process chamber in the first horizontal direction along the second planar face such that a first offset space is formed below the first process chamber and beside an adjacent sidewall of the second process chamber, and has a width larger than a first value and smaller than a half of a width of the first process chamber in the first horizontal direction along the second planar face;
- first and second exhaust lines respectively connecting first and second exhaust ports formed in bottoms of the first and second process chambers to corresponding vacuum exhaust sections, the first exhaust line extending downward through the first offset space and having a width of the first value in the first horizontal direction along the second planar face;
- and
- a transfer mechanism disposed in the transfer chamber, and configured to transfer a target substrate to and from the load lock chamber and the first and second process chambers,
- wherein the first exhaust port is disposed at a substantial center of the first process chamber, and a gas convergence portion is formed below the firstexhaust port, and the first exhaust line includes a first portion extending horizontally from the gas convergence portion to the first offset space, and a second portion extending downward from the first portion through the first offset space.
5 more elements
Dependencies are inferred from the claim text.