Method and apparatus for DC offset cancellation in amplifiers

A circuit for canceling DC offset errors in cascaded amplifiers, said circuit comprising:

• a plurality of any of analog voltage and analog circuit amplifier stages arranged in any of cascaded and parallel configurations;
• a feedback path around a given amplifier, wherein said feedback path comprises a feedback comparator and digital logic, wherein said digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching;
• and
• a switch operatively connected at a differential input of said amplifier to short both input terminals of said amplifier,
• wherein said fixed switching is performed on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at said input of said amplifier, and
• wherein said modulated switching is performed on at least one lower least significant bit (LSB) of all bits used to vary said any of said DC offset voltage and current.

A system for canceling DC offset errors in cascaded amplifiers, said system comprising:

• a signal generator;
• a plurality of any of analog voltage and analog circuit amplifiers stages arranged in any of cascaded and parallel configurations and adapted to receive signals from said signal generator;
• a feedback path around a given amplifier, wherein said feedback path comprises a feedback comparator and digital logic, wherein said digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching, wherein said feedback comparator and said digital logic are configured around each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein said feedback comparator and said digital logic are shared for each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein a first stage in a chain of amplifiers is calibrated first, followed by a second stage amplifier, up to a Nth stage in a cascade of N amplifier stages, wherein said adaptive search algorithm comprises any of a binary search algorithm and a linear search algorithm, wherein in said binary search algorithm, a most significant bit (MSB) is first asserted;
• and
• a switch operatively connected at a differential input of said amplifier to short both input terminals of said amplifier,
• wherein said fixed switching is performed on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at said input of said amplifier,
• wherein said modulated switching is performed on at least one lower least significant bit (LSB) of all bits used to vary said any of said DC offset voltage and current, and wherein the modulating process is performed by any of a carry out signal of an accumulator clocked with a high-speed clock and by an output signal of a digital sigma-delta modulator.