Through-core self-test with multiple loopbacks
AssigneeRambus Inc.
InventorsAkash Bansal, Michael Sobelman, Simon Li, Donald A. Draper
Life of this patent
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AssigneeRambus Inc.
InventorsAkash Bansal, Michael Sobelman, Simon Li, Donald A. Draper
Estimating the term…
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.
An integrated circuit device comprising:
An integrated circuit device comprising:
A method of testing an integrated circuit device, the method comprising:
Computer-readable media having information embodied therein that constitutes a representation of an apparatus comprising:
An integrated circuit device comprising:
Dependencies are inferred from the claim text.