Low-power SRAM memory cell
OwnerYen-Jen Chang, Feipei Lai +1inventors
InventorsYen-Jen Chang, Feipei Lai, Chia-Lin Yang
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Abstract
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.
Claims12
A semiconductor memory cell comprising:
- a first inverter including a pair of CMOS field effect transistors that are coupled in series, that respectively have gate terminals, and that further have a first common connection node, said first inverter being adapted to be coupled between a power terminal and a ground terminal;
- a second inverter including a pull-up transistor adapted to be coupled to the power terminal, and a pull-down transistor coupled in series to said pull-up transistor, said pull-up and pull-down transistors having a second common connection node coupled to said gate terminals of said field effect transistors, and respectively having gate terminals coupled to said first common connection node;
- first and second read bit lines;
- first and second read access transistors, each of which selectively couples a respective one of said first and second read bit lines to a respective one of said first and second common connection nodes;
- a read word line coupled to said first and second read access transistors to control turn on and turn off activities of said first and second read access transistors;
- a switching transistor for selectively coupling said second inverter to the ground terminal;
- a write bit line;
- a write access transistor for selectively coupling said second common connection node to said write bit line;
- and
- a write word line coupled to said write access transistor to control turn on and turn off activities of said write access transistor.
A method of writing data to a semiconductor memory cell, the semiconductor memory cell including cross-coupled first and second inverters, each of the first and second inverters having a pull-up transistor and a pull-down transistor that is coupled in series to the pull-up transistor, the pull-up and pull-down transistors of each of the first and second inverters being coupled between a power terminal and a ground terminal, the first and second inverters respectively having first and second common connection nodes at junctions of the pull-up and pull-down transistors, said method comprising:
- a) providing a write bit line to be coupled selectively to the second common connection node;
- b) pre-charging the write bit line;
- c) breaking electrical connection between the second inverter and the ground terminal;
- and
- d) without changing a logic state of the write bit line, making electrical connection between the write bit line and the second common connection node to write a data bit with a write value of ‘0’ to the semiconductor memory cell.
A semiconductor memory cell comprising:
- a first inverter including a pair of CMOS field effect transistors that are coupled in series, that respectively have gate terminals, and that further have a first common connection node, said first inverter being adapted to be coupled between a power terminal and a ground terminal;
- a second inverter including a pull-up transistor adapted to be coupled to the power terminal, and a pull-down transistor coupled in series to said pull-up transistor, said pull-up and pull-down transistors having a second common connection node coupled to said gate terminals of said field effect transistors, and respectively having gate terminals coupled to said first common connection node;
- a bit line;
- read and write access transistors, each of which selectively couples said bit line to said second common connection node;
- a read word line coupled to said read access transistor to control turn on and turn off activities of said read access transistor;
- a write word line coupled to said write access transistor to control turn on and turn off activities of said write access transistor;
- and
- a switching transistor for selectively coupling said second inverter to the ground terminal.
Dependencies are inferred from the claim text.