US 7,337,100 B1Granted

Physical resynthesis of a logic design

AssigneeAltera Corporation

InventorsMichael D. Hutton, Joachim Pistorius, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Yean-Yow Hwang

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Abstract

A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

Claims39

Dependent claims

A method comprising:

providing a high-level design language representation of an integrated circuit design;
obtaining a first netlist for the integrated circuit design from a first synthesis tool;
unmapping the first netlist to obtain a gate-level representation of the first netlist;
resynthesizing the integrated circuit design using a second synthesis tool to generate a second netlist;
and
generating a final integrated circuit design using the second netlist, the final integrated circuit design to be used in producing an integrated circuit,
wherein the resynthesizing step further includes:
executing a partial fit against the gate-level representation of the first netlist to determine delays for the gate-level representation;
executing a resynthesis of the partially-fit gate-level representation using the gate level representation from the first tool, the determined appropriate delays from the second tool, and a different synthesis algorithm than was used to generate the first netlist, and identifying portions of the gate-level representation as timing-critical portions or timing non-critical portions;
and
remapping the timing-critical portions of the resynthesized gate level representation with a bias toward timing improvements and concurrently remapping the timing non-critical portions with a bias toward area minimization to generate the second netlist, the second netlist being at least partially optimized for both performance and area requirements of the integrated circuit design.

8 more elements

A design resynthesis system, comprising:

a processor;
and
a storage medium coupled with the processor and including instructions capable of being executed by the processor, the instructions when executed operable to:
receive a first netlist for an integrated circuit design from an external synthesis tool;
unmap a first netlist for an integrated circuit design to obtain a gate-level representation of the first netlist;
execute a partial fit against the gate-level representation of the first netlist to determine delays for the gate-level representation;
execute a resynthesis of the partially-fit gate-level representation using the gate level representation from the external synthesis tool, the determined appropriate delays from the design resynthesis system, and a different synthesis algorithm than was used to generate the first netlist, and identify portions of the gate-level representation as timing-critical portions or timing non-critical portions;
remap the timing-critical portions of the resynthesized gate level representation with a bias toward timing improvements and concurrently remapping the timing non-critical portions with a bias toward area minimization to generate the second netlist, the second netlist being at least partially optimized for both performance and area requirements of the integrated circuit design;
and
generate a final integrated circuit design using the second netlist, the final integrated circuit design to be used in producing an integrated circuit.

7 more elements

A computer program product embedded in a computer readable medium for generating an integrated circuit design, comprising:

computer program code for providing a high-level design language representation of an integrated circuit design;
computer program code for obtaining a first netlist for the integrated circuit design from an external synthesis tool;
computer program code for unmapping the first netlist to obtain a gate-level representation of the first netlist;
computer program code for executing a partial fit against the gate-level representation of the first netlist to determine delays for the gate-level representation;
computer program code for executing a resynthesis of the partially-fit gate-level representation using the gate level representation from the external synthesis tool, the determined appropriate delays, and a different synthesis algorithm than was used to generate the first netlist, and identifying portions of the gate-level representation as timing-critical portions or timing non-critical portions;
and
computer program code for remapping the timing-critical portions of the resynthesized gate level representation with a bias toward timing improvements and concurrently remapping the timing non-critical portions with a bias toward area minimization to generate the second netlist, the second netlist being at least partially optimized for both performance and area requirements of the integrated circuit design;
and
computer program code for generating a final integrated circuit design using the second netlist, the final integrated circuit design to be used in producing an integrated circuit.

6 more elements

Dependencies are inferred from the claim text.