US 7,336,336 B2Granted

Thin film transistor array substrate, method of fabricating the same, liquid crystal display panel having the same and fabricating method thereof

AssigneeLG. Philips Co., Ltd.

InventorsSoon Sung Yoo, Youn Gyoung Chang, Heung Lyul Cho, Seung Hee Nam

Life of this patent

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Abstract

A substrate has intersecting gate and data lines with a gate insulating film therebetween, a thin film transistor provided at an intersection of the gate and data lines, a pixel electrode connected to the transistor, a pad connected to a signal line via a contact hole and containing a transparent conductive film, and a protective film overlapping a color filter array substrate to expose the film. The contact hole exposes the end of the pad and/or signal line and an adjacent area. A gate electrode, source and drain electrodes, and a contact electrode are formed from first, second, and third conductive layers, respectively. A contact hole exposes the first conductive layer of one transistor and an adjacent portion of the second conductive layer of another transistor. The contact electrode connects the exposed first and second conductive layers. Only three mask processes are used in fabricating the substrate.

Claims11

Dependent claims

A method of fabricating a liquid crystal display panel, the method comprising:

providing a color filter array substrate;
and
providing a thin film transistor array substrate opposed to the color filter array substrate and having:
a gate line and a data line intersecting each other on a lower substrate with a gate insulating film therebetween,
a thin film transistor provided at an intersection between the gate line and the data line,
a pixel electrode connected to the thin film transistor,
a pad connected to a signal line via a contact hole, the signal line including the gate line or the data line, the pad formed from a transparent conductive film, and
a protective film provided at least in an area overlapping with the color filter array substrate;
joining the thin film transistor array substrate with the color filter array substrate by a sealant to expose a pad area including a gate pad and a data pad;
and
removing the protective film using the color filter array substrate as a mask to expose the transparent conductive film of the pad area,
wherein the contact hole exposes an end of at least one of the pad and the signal line as well as an area adjacent thereto.

9 more elements

A method of fabricating a thin film transistor array substrate, the method comprising:

providing gate patterns including a gate line, a gate electrode, a gate pad and data pad, and a pixel electrode on the substrate, the gate patterns including a transparent conductive film;
providing a semiconductor pattern and a gate insulating pattern on the substrate provided with the gate patterns and the pixel electrode;
providing a data pattern including a data line, a source electrode and a drain electrode connected, via the contact hole, to the data pad on the substrate provided with the semiconductor pattern and the gate insulating pattern;
providing a protective film on the entire substrate to protect a thin film transistor formed by the gate pattern, the semiconductor pattern, the gate insulating pattern, and the data pattern;
providing an alignment film on the protective film in an area other than a pad area, the pad area including the gate pad and the data pad;
and
removing the protective film covering the pad area using the alignment film as a mask, thereby exposing the transparent conductive film of the pad area,
wherein the contact hole exposes an end of at least one of the data pad and the data line as well as an area adjacent thereto.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/964,485Filed 13 Oct 2004
Priority: KR 10-2003-007140314 Oct 2003
Published: US 2005/0078264 A114 Apr 2005
Granted: 26 Feb 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G02F 1/136204
Active matrix addressed cells: arrangements to prevent high voltage or static electricity failures
G02F 1/1345
Constructional arrangements; Manufacturing methods: conductors connecting electrodes to cell terminals
H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks
H10D 86/443
Interconnections, e.g. scanning lines: adapted for preventing breakage, peeling or short circuiting