Configurable integrated circuit capacitor array using via mask layers
AssigneesTriad Semiconductor, Inc., ViASIC, Inc.
InventorsDavid Ihme, James C. Kemerling, William D. Cox
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Abstract
A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.
Claims26
A semiconductor device comprising:
- a capacitor array comprising a plurality of capacitor tiles, each capacitor tile comprising at least one capacitor;
- a first plurality of first metal routing tracks overlaying the at least one capacitor of each capacitor tile;
- a second plurality of second metal routing tracks also overlaying the at least one capacitor of each capacitor tile, with the second metal routing tracks crossing over the first metal routing tracks;
- an orientation of the first metal routing tracks being alternated from one capacitor tile to the next;
- and an orientation of the second metal routing tracks being alternated from one capacitor tile to the next;
- each capacitor within a capacitor tile having:
- a first electrical connection to a first of said first metal routing tracks and a second electrical connection to a second of said first metal routing tracks;
- and
- a plurality of vias all belonging to a single layer within the semiconductor device, said plurality of vias connecting some of the second metal routing tracks to some of the first metal routing tracks, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor.
A semiconductor device comprising:
- a two-dimensional arrangement of capacitor tiles, each capacitor tile comprising:
- at least one capacitor;
- a first plurality of first metal routing tracks overlaying the at least one capacitor;
- a second plurality of second metal routing tracks also overlaying the at least one capacitor, with the second metal routing tracks crossing over the first metal routing tracks,
- a first electrical connection from said at least one capacitor to a first of said first metal routing tracks;
- and
- a second electrical connection from said at least one capacitor to a second of said first metal routing tracks;
- wherein:
- an orientation of the first metal routing tracks is alternated from one capacitor tile to the next;
- an orientation of the second metal routing tracks is alternated from one capacitor tile to the next;
- and
- a plurality of vias all belonging to a single layer within the semiconductor device connect some of the second metal routing tracks to some of the first metal routing tracks, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor.
Dependencies are inferred from the claim text.